J. Semicond. > 2014, Volume 35 > Issue 1 > 014006, doi: 10.1088/1674-4926/35/1/014006
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SEMICONDUCTOR DEVICES

Design of two-terminal PNPN diode for high-density and high-speed memory applications

Xiaodong Tong, Hao Wu, Qingqing Liang, Huicai Zhong, Huilong Zhu, Chao Zhao and Tianchun Ye

+ Author Affiliations

 Corresponding author: Tong Xiaodong, Email:tongxiaodong@ime.ac.cn

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Abstract: A vertical two-terminal silicon PNPN diode is presented for use in a high-density memory cell. The device design for high-speed operations was studied with experiments and calibrated simulations, which proves that the proposed memory cell can be operated at nanosecond range. The static and dynamic power dissipations were also studied, which indicated the availability of the proposed memory cell for VLSI applications. Moreover, the memory cell is compatible with CMOS process, has little impact from process variation, and has good reliability.

Key words: PNPN diode, memory cell, high-density



[1]
Kuhn K J. Considerations for ultimate CMOS scaling. IEEE Trans Electron Devices, 2012, 59(7):1813 doi: 10.1109/TED.2012.2193129
[2]
Asenov A, Kaya S, Brown A R. Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edgeroughness. IEEE Trans Electron Devices, 2003, 50(5):1254 doi: 10.1109/TED.2003.813457
[3]
Kampen C, Evanschitzky P, Burenkov A, et al. Lithographyinduced layout variations in 6-t SRAM cells. International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2010:149
[4]
Liang J, Gnana R, Jeyasingh D, et al. An ultra-low reset current cross-point phase change memory with carbon nanotube electrodes. IEEE Trans Electron Devices, 2012, 59(4):1155 doi: 10.1109/TED.2012.2184542
[5]
Chaudhry A. Interconnects for nanoscale MOSFET technology:a review. Journal of Semiconductors, 2012, 34(6): http://www.jos.ac.cn/bdtxbcn/ch/reader/view_abstract.aspx?file_no=12120101&flag=1
[6]
Gibbons J F. A critique of the theory of p-n-p-n devices. IEEE Trans Electron Devices, 1964, 11(9):406 doi: 10.1109/T-ED.1964.15352
[7]
Tserng H Q, Plumlee H R. The turn-on delay time of silicon p-n-p-n switches. Proc IEEE, 1970, 58(5):792 doi: 10.1109/PROC.1970.7736
[8]
Synopsys Inc. TCAD Sentaurus user manual. 2010
[9]
Heremans P L. Fast turn-off of two-terminal double heterojunction optical thyristors. Appl Phys Lett, 1992, 61(11):1326 doi: 10.1063/1.107581
[10]
Tsai M F, Tsai J H, Fan M L, et al. Variation tolerant CLSAs for nanoscale bulk-CMOS and FinFET SRAM. APCCAS, 2012:471
[11]
Ronse K, Jansen P, Gronheid R, et al. Lithography options for the 32 nm half pitch node and beyond. IEEE Trans Circuits Syst Ⅰ:Regular Papers, 2009, 56(8):1884 doi: 10.1109/TCSI.2009.2028417
[12]
Akashe S, Rastogi S, Sharma S. Specific power illustration of proposed 7T SRAM with 6T SRAM using 45 nm technology. ICONSET, 2011
[13]
Razavipour G, Afzali-Kusha A, Pedram M. Design and analysis of two low-power SRAM cell structures. IEEE Trans VLSI, 2009, 17(10):1551 doi: 10.1109/TVLSI.2008.2004590
Fig. 1.  (a) The structure of the proposed memory cell, and (b) the hysteresis curve of the new memory cell and the write voltage pulses.

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Fig. 2.  The process flow of the PNPN diode memory cell.

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Fig. 3.  The measured hysteresis curve and the SEM view of Cell 1. Note that at $V_{\rm AC}$ $>$ 1.6 V, the $I_{\rm A}$ is constant because the actual current through the cell hits the compliance level of the SMU.

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Fig. 4.  (a) The pulsed measuring circuit and the low speed measure, (b) the increased frequency write-1 measure, in which delay time was observed.

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Fig. 5.  (a) The measured hysteresis curve of Cell 2 and its simulated hysteresis curve. Note that at $V_{\rm AC}$ $>$ 1 V, the $I_{\rm A}$ is constant because the actual current through the cell hits the compliance of the SMU. (b) The write-1 operation measure of Cell 2

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Fig. 6.  (a) The write-1 simulation indicates that Cell 2 can be operated at ns level with an available voltage and (b) the simulated $T_{\rm dr}$–$V_{\rm H}$ trend of Cell 2.

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Fig. 7.  (a) The measured $V_{\rm LU}$ distribution and (b) the simulated $T_{\rm dr}$–$V_{\rm LU}$ relationship.

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Fig. 8.  (a) The simulated write-1 operations with different $V_{\rm holds}$, and (b) the simulated $T_{\rm df}$–$V_{\rm hold}$ trend.

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Fig. 9.  (a) The write-0 measures of Cell 2, and (b) the hysteresis curve of the Cell 3 in comparison with Cell 2 and the illustration of the punch-trough design.

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Fig. 10.  (a) The write-0 measures of Cell 3, and (b) the ns-level write-0 operation simulation of Cell 3.

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Fig. 11.  (a) The process variation and (b) the reliability measure of Cell 3.

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Table 1.   The studied cells in the optimization patch.

Table 2.   The main performance of the proposed cell and the 6T SRAM cell in 45 nm process.
[1]
Kuhn K J. Considerations for ultimate CMOS scaling. IEEE Trans Electron Devices, 2012, 59(7):1813 doi: 10.1109/TED.2012.2193129
[2]
Asenov A, Kaya S, Brown A R. Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edgeroughness. IEEE Trans Electron Devices, 2003, 50(5):1254 doi: 10.1109/TED.2003.813457
[3]
Kampen C, Evanschitzky P, Burenkov A, et al. Lithographyinduced layout variations in 6-t SRAM cells. International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2010:149
[4]
Liang J, Gnana R, Jeyasingh D, et al. An ultra-low reset current cross-point phase change memory with carbon nanotube electrodes. IEEE Trans Electron Devices, 2012, 59(4):1155 doi: 10.1109/TED.2012.2184542
[5]
Chaudhry A. Interconnects for nanoscale MOSFET technology:a review. Journal of Semiconductors, 2012, 34(6): http://www.jos.ac.cn/bdtxbcn/ch/reader/view_abstract.aspx?file_no=12120101&flag=1
[6]
Gibbons J F. A critique of the theory of p-n-p-n devices. IEEE Trans Electron Devices, 1964, 11(9):406 doi: 10.1109/T-ED.1964.15352
[7]
Tserng H Q, Plumlee H R. The turn-on delay time of silicon p-n-p-n switches. Proc IEEE, 1970, 58(5):792 doi: 10.1109/PROC.1970.7736
[8]
Synopsys Inc. TCAD Sentaurus user manual. 2010
[9]
Heremans P L. Fast turn-off of two-terminal double heterojunction optical thyristors. Appl Phys Lett, 1992, 61(11):1326 doi: 10.1063/1.107581
[10]
Tsai M F, Tsai J H, Fan M L, et al. Variation tolerant CLSAs for nanoscale bulk-CMOS and FinFET SRAM. APCCAS, 2012:471
[11]
Ronse K, Jansen P, Gronheid R, et al. Lithography options for the 32 nm half pitch node and beyond. IEEE Trans Circuits Syst Ⅰ:Regular Papers, 2009, 56(8):1884 doi: 10.1109/TCSI.2009.2028417
[12]
Akashe S, Rastogi S, Sharma S. Specific power illustration of proposed 7T SRAM with 6T SRAM using 45 nm technology. ICONSET, 2011
[13]
Razavipour G, Afzali-Kusha A, Pedram M. Design and analysis of two low-power SRAM cell structures. IEEE Trans VLSI, 2009, 17(10):1551 doi: 10.1109/TVLSI.2008.2004590

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    Received: 13 June 2013 Revised: 26 July 2013 Online: Published: 01 January 2014

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      Article Navigation >  Journal of Semiconductors  > 2014  >  35(1): 014006
      Xiaodong Tong, Hao Wu, Qingqing Liang, Huicai Zhong, Huilong Zhu, Chao Zhao, Tianchun Ye. Design of two-terminal PNPN diode for high-density and high-speed memory applications[J]. Journal of Semiconductors, 2014, 35(1): 014006. doi: 10.1088/1674-4926/35/1/014006 X D Tong, H Wu, Q Q Liang, H C Zhong, H L Zhu, C Zhao, T C Ye. Design of two-terminal PNPN diode for high-density and high-speed memory applications[J]. J. Semicond., 2014, 35(1): 014006. doi: 10.1088/1674-4926/35/1/014006.Export: BibTex EndNote
      Citation:
      Xiaodong Tong, Hao Wu, Qingqing Liang, Huicai Zhong, Huilong Zhu, Chao Zhao, Tianchun Ye. Design of two-terminal PNPN diode for high-density and high-speed memory applications[J]. Journal of Semiconductors, 2014, 35(1): 014006. doi: 10.1088/1674-4926/35/1/014006

      X D Tong, H Wu, Q Q Liang, H C Zhong, H L Zhu, C Zhao, T C Ye. Design of two-terminal PNPN diode for high-density and high-speed memory applications[J]. J. Semicond., 2014, 35(1): 014006. doi: 10.1088/1674-4926/35/1/014006.
      Export: BibTex EndNote
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      Design of two-terminal PNPN diode for high-density and high-speed memory applications

      doi: 10.1088/1674-4926/35/1/014006

      • Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

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      • Corresponding author: Tong Xiaodong, Email:tongxiaodong@ime.ac.cn
      • Received Date: 2013-06-13
      • Revised Date: 2013-07-26
      • Published Date: 2014-01-01

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