Fig. 1.
The schematic cross section of the investigated ps-LDMOS.
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Hao Wang, Siyang Liu, Weifeng Sun, Tingting Huang. Research and optimization of the ESD response characteristic in a ps-LDMOS transistor[J]. Journal of Semiconductors, 2014, 35(1): 014010. doi: 10.1088/1674-4926/35/1/014010
H Wang, S Y Liu, W F Sun, T T Huang. Research and optimization of the ESD response characteristic in a ps-LDMOS transistor[J]. J. Semicond., 2014, 35(1): 014010. doi: 10.1088/1674-4926/35/1/014010.
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Research and optimization of the ESD response characteristic in a ps-LDMOS transistor
doi: 10.1088/1674-4926/35/1/014010
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Abstract
The ESD response characteristic in a p-type symmetric lateral DMOS (ps-LDMOS) has been investigated. The experimental results show that the ps-LDMOS has weak ESD robustness due to an absence of the "snapback" characteristic. In addition, the location of the hot spot changes little for the special device. The method for reducing the lattice temperature of the hot spot can be used to enhance the ESD capacity of the ps-LDMOS, thereby, a novel and easily-achievable ps-LDMOS structure with a p-type lightly doped drain (p-LDD) has been proposed. The special region p-LDD lowers the electric field at the edge of the poly gate, making the whole distribution of the surface electric field more uniform. Therefore, the ESD robustness is improved two times and no obvious change of other electric parameters is introduced.-
Keywords:
- ESD response characteristic,
- ESD robustness,
- ps-LDMOS,
- p-LDD
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References
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