J. Semicond. > 2014, Volume 35 > Issue 10 > 105011, doi: 10.1088/1674-4926/35/10/105011
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SEMICONDUCTOR INTEGRATED CIRCUITS

Design and analysis of a dual mode CMOS field programmable analog array

Xiaoyan Cheng1, 2, Haigang Yang1, , Tao Yin1, Qisong Wu1, Hongfeng Zhang1, 2 and Fei Liu1

+ Author Affiliations

 Corresponding author: Yang Haigang, Email:yanghg@mail.ie.ac.cn

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Abstract: This paper presents a novel field-programmable analog array (FPAA) architecture featuring a dual mode including discrete-time (DT) and continuous-time (CT) operation modes, along with a highly routable connection boxes (CBs) based interconnection lattice. The dual mode circuit for the FPAA is capable of achieving targeted optimal performance in different applications. The architecture utilizes routing switches in a CB not only for the signal interconnection purpose but also for control of the electrical charge transfer required in switched-capacitor circuits. This way, the performance of the circuit in either mode shall not be hampered with adding of programmability. The proposed FPAA is designed and implemented in a 0.18 μm standard CMOS process with a 3.3 V supply voltage. The result from post-layout simulation shows that a maximum bandwidth of 265 MHz through the interconnection network is achieved. The measured results from demonstrated examples show that the maximum signal bandwidth of up to 2 MHz in CT mode is obtained with the spurious free dynamic range of 54 dB, while the signal processing precision in DT mode reaches 96.4%.

Key words: field-programmable gate array, field-programmable analog array, configurable analog block, rail-to-rail, biquadratic filters



[1]
Sivilotti M A. A dynamically configurable architecture for prototyping analog circuits. Proceedings of the Fifth MIT Conference on Advanced Research in VLSI, MIT, 1988:237
[2]
Becker J, Henrici F, Trendelenburg S, et al. A field-programmable analog array of 55 digitally tunable OTAs in a hexagonal lattice. IEEE J Solid-State Circuits, 2008, 43(12):2759 doi: 10.1109/JSSC.2008.2005697
[3]
Stoica A, Zebulum R, Keymeulen D, et al. Reconfigurable VLSI architectures for evolvable hardware:from experimental field programmable transistor arrays to evolution-oriented chips. IEEE Trans Very Large Scale Integration (VLSI) Systems, 2001, 9(1):227 doi: 10.1109/92.920839
[4]
Lee E K F, Gulak P G. A CMOS field-programmable analog array. IEEE J Solid-State Circuits, 1991, 26(12):1860 doi: 10.1109/4.104162
[5]
Basu A, Brink S, Schlottmann C, et al. A floating-gate-based field-programmable analog array. IEEE J Solid-State Circuits, 2010, 45(9):1781 doi: 10.1109/JSSC.2010.2056832
[6]
Luo J. Circuit design and routing for field programmable analog arrays. Doctor of Philosophy, Department of Electrical and Computer Engineering, University of Maryland, 2005
[7]
Cheng X Y, Yin T, Wu Q S, et al. A CMOS FIELD programmable analog array for intelligent sensory application. 23rd International Conference on Field Programmable Logic and Applications, Porto, Portugal, 2013:2
[8]
Hasler P E, Twigg C M. An OTA-based large-scale field programmable analog array (FPAA) for faster on-chip communication and computation. IEEE International Symposium on Circuits and Systems, 2007:177
[9]
Brown T W, Fie T S Z, Hakkarainen M. Prediction and characterization of frequency dependent MOS switch linearity and the design implications. CICC, 2006 http://ieeexplore.ieee.org/document/4114948/
[10]
Gregorian R, Temes G C. Analog MOS integrated circuits for signal processing. John Wiley & Sons, 1986
[11]
Mohan P V A, Ramachandran V, Swamy M N S. Switched capacitor filters:theory, analysis and design. Prentice Hall, 1995
[12]
Moldovan L, Li H H. A rail-to-rail, constant gain, buffered op-amp for real time video applications. IEEE J Solid-State Circuits, 1997, 32(2):169 doi: 10.1109/4.551908
[13]
Hogervorst R, Tero J P, Eschauzier R G H, et al. A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries. IEEE J Solid-State Circuits, 1994, 29(12):1505 doi: 10.1109/4.340424
[14]
Carrillo J M, Duque-Carrillo J F, Torelli G, et al. Constant-gm constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries. IEEE J Solid-State Circuits, 2003, 38(8):1364 doi: 10.1109/JSSC.2003.814430
[15]
Fu W H, Jiang J, Qin X, et al. A reconfigurable analog processor using coarse-grained, heterogeneous configurable analog blocks for field programmable mixed-signal processing. Analog Integr Circuits Signal Process, 2011, 2011(68):93
[16]
Wunderlich R B, Adil F, Hasler P. Floating gate-based field programmable mixed-signal array. IEEE Trans Very Large Scale Integration (VLSI) System, 2013, 21(8):1496 doi: 10.1109/TVLSI.2012.2211049
Fig. 1.  Conceptual block diagram of FPAA

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Fig. 2.  (a) An analog circuit and its mapping in the target traditional FPAA architecture and (b) the variation of on-resistance $R_{\rm on}$ and parasitic capacitance $C_{\rm p}$ of a CMOS switch with $V_{\rm in}$ sweeping from 0 to 3.3 V

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Fig. 3.  (a) Actual circuit mapping in the FPAA with parasitic RC modeling of CMOS switches. (b) Routing delay of a path line in CMOS switch matrix interconnection network. (c) The THD comparison of FPAA versus ASIC

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Fig. 4.  (a) The high-level architecture of FPAA. (b) Structure of a CAB and zoomed view for a connection box (CB)

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Fig. 5.  Four configurations of a SCB. (a) Off configuration. (b) Capacitor configuration. (c) Positive resistor configuration. (d) Negative resistor configuration

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Fig. 6.  The proposed architecture of FPAA for highly routable CB utilization in single column

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Fig. 7.  The schematic of rail to rail low power class-AB amplifier

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Fig. 8.  Input stage gm versus $V_{\rm icm}$ of proposed OPA

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Fig. 9.  (a) The circuit diagram of reconstruction filter and (b) the architecture of configuration bit stream registers

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Fig. 10.  Die microphotograph of the fabricated FPAA

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Fig. 11.  Matlab GUI configuration tool

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Fig. 12.  (a) Circuit diagram of two stages PGA and (b) PGA mapped in FPAA

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Fig. 13.  Test results of PGA. (a) Transient output waveform and (b) power spectral density of PGA with an input sinusoidal wave of 2 MHz @ gain = 4

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Fig. 14.  (a) The schematic of SC adder circuit and (b) the adder circuit mapped in FPAA

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Fig. 15.  (a) Transient test result with 1 MHz sample clock and (b) precision test results of adder circuit

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Fig. 16.  (a) Programmable biquadratic switched capacitor band pass filter and (b) the band pass filter mapped in FPAA

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Fig. 17.  Measured frequency responses of the second order programmable band pass filters varying with $f_{\rm c}$

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Fig. 18.  Power spectral density of bandpass filter with an input sinusoidal wave of 50 kHz and $V_{\rm pp}$ = 2 V @ $f_{\rm s}$ = 1 MHz

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Fig. 19.  (a) The schematic of second order switched capacitor high pass filter and (b) the high pass filter mapped in FPAA

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Fig. 20.  Measurement of programmable high pass filters transfer functions with different corner frequencies

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Table 1.   Performances of rail to rail amplifier in unity-gain inverting configuration with 32 pF || 800 Ω load. (Technology: 0.18 $\mu $m CMOS, $V_{\rm DD}$ = 3.3 V)

Table 2.   Comparison to prior designs
[1]
Sivilotti M A. A dynamically configurable architecture for prototyping analog circuits. Proceedings of the Fifth MIT Conference on Advanced Research in VLSI, MIT, 1988:237
[2]
Becker J, Henrici F, Trendelenburg S, et al. A field-programmable analog array of 55 digitally tunable OTAs in a hexagonal lattice. IEEE J Solid-State Circuits, 2008, 43(12):2759 doi: 10.1109/JSSC.2008.2005697
[3]
Stoica A, Zebulum R, Keymeulen D, et al. Reconfigurable VLSI architectures for evolvable hardware:from experimental field programmable transistor arrays to evolution-oriented chips. IEEE Trans Very Large Scale Integration (VLSI) Systems, 2001, 9(1):227 doi: 10.1109/92.920839
[4]
Lee E K F, Gulak P G. A CMOS field-programmable analog array. IEEE J Solid-State Circuits, 1991, 26(12):1860 doi: 10.1109/4.104162
[5]
Basu A, Brink S, Schlottmann C, et al. A floating-gate-based field-programmable analog array. IEEE J Solid-State Circuits, 2010, 45(9):1781 doi: 10.1109/JSSC.2010.2056832
[6]
Luo J. Circuit design and routing for field programmable analog arrays. Doctor of Philosophy, Department of Electrical and Computer Engineering, University of Maryland, 2005
[7]
Cheng X Y, Yin T, Wu Q S, et al. A CMOS FIELD programmable analog array for intelligent sensory application. 23rd International Conference on Field Programmable Logic and Applications, Porto, Portugal, 2013:2
[8]
Hasler P E, Twigg C M. An OTA-based large-scale field programmable analog array (FPAA) for faster on-chip communication and computation. IEEE International Symposium on Circuits and Systems, 2007:177
[9]
Brown T W, Fie T S Z, Hakkarainen M. Prediction and characterization of frequency dependent MOS switch linearity and the design implications. CICC, 2006 http://ieeexplore.ieee.org/document/4114948/
[10]
Gregorian R, Temes G C. Analog MOS integrated circuits for signal processing. John Wiley & Sons, 1986
[11]
Mohan P V A, Ramachandran V, Swamy M N S. Switched capacitor filters:theory, analysis and design. Prentice Hall, 1995
[12]
Moldovan L, Li H H. A rail-to-rail, constant gain, buffered op-amp for real time video applications. IEEE J Solid-State Circuits, 1997, 32(2):169 doi: 10.1109/4.551908
[13]
Hogervorst R, Tero J P, Eschauzier R G H, et al. A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries. IEEE J Solid-State Circuits, 1994, 29(12):1505 doi: 10.1109/4.340424
[14]
Carrillo J M, Duque-Carrillo J F, Torelli G, et al. Constant-gm constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries. IEEE J Solid-State Circuits, 2003, 38(8):1364 doi: 10.1109/JSSC.2003.814430
[15]
Fu W H, Jiang J, Qin X, et al. A reconfigurable analog processor using coarse-grained, heterogeneous configurable analog blocks for field programmable mixed-signal processing. Analog Integr Circuits Signal Process, 2011, 2011(68):93
[16]
Wunderlich R B, Adil F, Hasler P. Floating gate-based field programmable mixed-signal array. IEEE Trans Very Large Scale Integration (VLSI) System, 2013, 21(8):1496 doi: 10.1109/TVLSI.2012.2211049

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    Received: 18 March 2014 Revised: 10 April 2014 Online: Published: 01 October 2014

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      Article Navigation >  Journal of Semiconductors  > 2014  >  35(10): 105011
      Xiaoyan Cheng, Haigang Yang, Tao Yin, Qisong Wu, Hongfeng Zhang, Fei Liu. Design and analysis of a dual mode CMOS field programmable analog array[J]. Journal of Semiconductors, 2014, 35(10): 105011. doi: 10.1088/1674-4926/35/10/105011 X Y Cheng, H G Yang, T Yin, Q S Wu, H F Zhang, F Liu. Design and analysis of a dual mode CMOS field programmable analog array[J]. J. Semicond., 2014, 35(10): 105011. doi: 10.1088/1674-4926/35/10/105011.Export: BibTex EndNote
      Citation:
      Xiaoyan Cheng, Haigang Yang, Tao Yin, Qisong Wu, Hongfeng Zhang, Fei Liu. Design and analysis of a dual mode CMOS field programmable analog array[J]. Journal of Semiconductors, 2014, 35(10): 105011. doi: 10.1088/1674-4926/35/10/105011

      X Y Cheng, H G Yang, T Yin, Q S Wu, H F Zhang, F Liu. Design and analysis of a dual mode CMOS field programmable analog array[J]. J. Semicond., 2014, 35(10): 105011. doi: 10.1088/1674-4926/35/10/105011.
      Export: BibTex EndNote
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      Design and analysis of a dual mode CMOS field programmable analog array

      doi: 10.1088/1674-4926/35/10/105011
      • 1.

        Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China

      • 2.

        University of Chinese Academy of Sciences, Beijing 100049, China

      Funds:

      the CAS/SAFEA International Partnership Program for Creative Research Teams and the National High Technology Research and Development Program of China 2012AA012301

      Project supported by the CAS/SAFEA International Partnership Program for Creative Research Teams and the National High Technology Research and Development Program of China (No. 2012AA012301)

      More Information
      • Corresponding author: Yang Haigang, Email:yanghg@mail.ie.ac.cn
      • Received Date: 2014-03-18
      • Revised Date: 2014-04-10
      • Published Date: 2014-10-01

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