SEMICONDUCTOR DEVICES

On substrate dopant engineering for ET-SOI MOSFETs with UT-BOX

Hao Wu, Miao Xu, Guangxing Wan, Huilong Zhu, Lichuan Zhao, Xiaodong Tong, Chao Zhao, Dapeng Chen and Tianchun Ye

+ Author Affiliations

 Corresponding author: Wu Hao, Email:wuhao@ime.ac.cn; Zhu Huilong, Email:zhuhuilong@ime.ac.cn

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Abstract: The importance of substrate doping engineering for extremely thin SOI MOSFETs with ultra-thin buried oxide (ES-UB-MOSFETs) is demonstrated by simulation. A new substrate/backgate doping engineering, lateral non-uniform dopant distributions (LNDD) is investigated in ES-UB-MOSFETs. The effects of LNDD on device performance, Vt-roll-off, channel mobility and random dopant fluctuation (RDF) are studied and optimized. Fixing the long channel threshold voltage (Vt) at 0.3 V, ES-UB-MOSFETs with lateral uniform doping in the substrate and forward back bias can scale only to 35 nm, meanwhile LNDD enables ES-UB-MOSFETs to scale to a 20 nm gate length, which is 43% smaller. The LNDD degradation is 10% of the carrier mobility both for nMOS and pMOS, but it is canceled out by a good short channel effect controlled by the LNDD. Fixing Vt at 0.3 V, in long channel devices, due to more channel doping concentration for the LNDD technique, the RDF in LNDD controlled ES-UB-MOSFETs is worse than in back-bias controlled ES-UB-MOSFETs, but in the short channel, the RDF for LNDD controlled ES-UB-MOSFET is better due to its self-adaption of substrate doping engineering by using a fixed thickness inner-spacer. A novel process flow to form LNDD is proposed and simulated.

Key words: extremely thin SOI (ETSOI)fully depleted SOI (FDSOI)short channel effect ultra thin BOX (UTBOX)



[1]
Cheng K, Khakifirooz A, Kulkarni P, et al. Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain. Symp VLSI Tech, 2009:212 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5200603
[2]
Cheng K, Khakifirooz A, Kulkarni P, et al. Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications. IEDM Tech Dig, 2009:49 http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=5424422
[3]
Fenouillet-Beranger C, Perreau P, Denorme S, et al. Impact of a 10 nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below. ESSDERC, 2009:89 http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=5325994
[4]
TCAD Sentaurus User Manual, D-2010. 12. , Synopsys
[5]
Barral V, Poiroux T, Andrieu F, et al. Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack. IEDM Tech Dig, 2007:61 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4418863
[6]
Packan P, Akbar S, Armstrong M, et al. High performance 32 nm logic technology featuring 2nd generation high-k + metal gate transistors. IEDM Tech Dig, 2009:41 http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=5424253
[7]
Andrieu F, Faynot O, Garros X, et al. Comparative scalability of PVD and CVD TiN on HfO2 as a metal gate stack for FDSOI CMOSFETs down to 25 nm gate length and width. IEDM Tech Dig, 2006:23.7 http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=4154284
[8]
Wettstein A, Penzin O, Lyumkis E, et al. Random dopant fluctuation modelling with the impedance field method. SISPAD, Boston, MA, USA, 2003:91 http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=1233645
Fig. 1.  The challenges for gate length scaling with reducing $V_{\rm t}$ by adjusting back bias. $V_{\rm t-lin}$ and $V_{\rm t-sat}$ here is the threshold voltage when $V_{\rm d}$ = 0.05 V and 1 V respectively.

Fig. 2.  Schematic structures of ES-UB-MOSFET fabrication process flow.

Fig. 3.  2D doping distributions in ES-UB-MOSFETs w/ RHP.

Fig. 4.  (a) Schematic of RHP charge induced charge in the gate interface. (b) 1-D integral of RHP charge induced equivalent back-bias.

Fig. 5.  The effects of RHP concentration, $C_{\rm RHP}$, and distance, $T_{\rm sub}$, between RHP top to the bottom of BOX on $V_{\rm t-sat}$ @ $V_{\rm bb}$ = 0 V in ideal structure simulation. (a) $V_{\rm t-sat}$ is more sensitive to the thicker RHP. (b) $V_{\rm t-sat}$ decreases with increasing of the total dosage, $C_{\rm RHP}$ $T_{\rm RHP}$ and saturates at 4 $\times$ 10$^{12}$ cm$^{-2}$. (c) $V_{\rm t-sat}$ versus $V_{\rm bb}$ curve under different substrate concentrations in ideal structure simulation.

Fig. 6.  (a) $I_{\rm D}$-$V_{\rm G}$ curves for ES-UB MOSFETs w/ RHP at $L_{\rm g}$ = 22 nm. Excellent SCE control was obtained. (b) $V_{\rm t}$ roll-off curves for ES-UB-MOSFETs, (1) w/ RHP with $V_{\rm bb}$ = 0 V and (2) w/o RHP with $V_{\rm bb}$ = 1.25 V for nMOS and $V_{\rm bb}$ = $-1.34$ for pMOS.

Fig. 7.  The comparison of (a) $I_{\rm on}$-$I_{\rm off}$ curves and (b) $I_{\rm eff}$-$I_{\rm off}$ curves of the ES-UB-MOSFETs for three conditions: (1) w/ RHP and $V_{\rm bb}$ = 0 V and (2) w/o RHP and $V_{\rm bb}$ = 0 V (3) w/o RHP and $V_{\rm bb}$ = 1.25 V for nMOS and $V_{\rm bb}$ = $-1.34$ V for pMOS.

Fig. 8.  (a) Mobility of electron and hole for ES-UB-MOSFETs with 30 nm gate length. $V_{\rm bb}$ stands for ES-UB-MOSFETs controlled by back bias, 0.8 V for nMOS and $-0.82$ V for pMOS. RHP stands for ETSOI controlled by RHP implant. The $V_{\rm t-sat}$ for each device is $\pm $0.3 V. (b) $I_{\rm d}$-$V_{\rm g}$ curves comparison for $V_{\rm bb}$ controlled ES-UB-MOSFETs and RHP controlled ES-UB-MOSFETs.

Fig. 9.  (a) Low-drain bias $I_{\rm d}$-$V_{\rm gs}$ and $V_{\rm g}$-$V_{\rm gs}$ curves from IFM simulation. Comparison of $V_{\rm t}$ for $V_{\rm bb}$ and/or RHP control ES-UB-MOSFETs and control devices with (b) 30 nm gate length and (c) 20 nm gate length. The $V_{\rm t-sat}$ for each device is $\pm $0.3 V.

Table 1.   Device parameters used in simulation.

[1]
Cheng K, Khakifirooz A, Kulkarni P, et al. Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain. Symp VLSI Tech, 2009:212 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5200603
[2]
Cheng K, Khakifirooz A, Kulkarni P, et al. Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications. IEDM Tech Dig, 2009:49 http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=5424422
[3]
Fenouillet-Beranger C, Perreau P, Denorme S, et al. Impact of a 10 nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below. ESSDERC, 2009:89 http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=5325994
[4]
TCAD Sentaurus User Manual, D-2010. 12. , Synopsys
[5]
Barral V, Poiroux T, Andrieu F, et al. Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack. IEDM Tech Dig, 2007:61 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4418863
[6]
Packan P, Akbar S, Armstrong M, et al. High performance 32 nm logic technology featuring 2nd generation high-k + metal gate transistors. IEDM Tech Dig, 2009:41 http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=5424253
[7]
Andrieu F, Faynot O, Garros X, et al. Comparative scalability of PVD and CVD TiN on HfO2 as a metal gate stack for FDSOI CMOSFETs down to 25 nm gate length and width. IEDM Tech Dig, 2006:23.7 http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=4154284
[8]
Wettstein A, Penzin O, Lyumkis E, et al. Random dopant fluctuation modelling with the impedance field method. SISPAD, Boston, MA, USA, 2003:91 http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=1233645
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    Received: 21 April 2014 Revised: 06 May 2014 Online: Published: 01 November 2014

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      Hao Wu, Miao Xu, Guangxing Wan, Huilong Zhu, Lichuan Zhao, Xiaodong Tong, Chao Zhao, Dapeng Chen, Tianchun Ye. On substrate dopant engineering for ET-SOI MOSFETs with UT-BOX[J]. Journal of Semiconductors, 2014, 35(11): 114006. doi: 10.1088/1674-4926/35/11/114006 H Wu, M Xu, G X Wan, H L Zhu, L C Zhao, X D Tong, C Zhao, D P Chen, T C Ye. On substrate dopant engineering for ET-SOI MOSFETs with UT-BOX[J]. J. Semicond., 2014, 35(11): 114006. doi: 10.1088/1674-4926/35/11/114006.Export: BibTex EndNote
      Citation:
      Hao Wu, Miao Xu, Guangxing Wan, Huilong Zhu, Lichuan Zhao, Xiaodong Tong, Chao Zhao, Dapeng Chen, Tianchun Ye. On substrate dopant engineering for ET-SOI MOSFETs with UT-BOX[J]. Journal of Semiconductors, 2014, 35(11): 114006. doi: 10.1088/1674-4926/35/11/114006

      H Wu, M Xu, G X Wan, H L Zhu, L C Zhao, X D Tong, C Zhao, D P Chen, T C Ye. On substrate dopant engineering for ET-SOI MOSFETs with UT-BOX[J]. J. Semicond., 2014, 35(11): 114006. doi: 10.1088/1674-4926/35/11/114006.
      Export: BibTex EndNote

      On substrate dopant engineering for ET-SOI MOSFETs with UT-BOX

      doi: 10.1088/1674-4926/35/11/114006
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      Project supported by the Opening Project of Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics and the China National S & T Major Project 02

      Project supported by the Opening Project of Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics and the China National S & T Major Project 02 

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