Fig. 1.
Architecture of the proposed PLC analog front end
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Huabin Chen, Jixuan Xiang, Xiangyan Xue, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren. An analog front end with a 12-bit 3.2-MS/s SAR ADC for a power line communication system[J]. Journal of Semiconductors, 2014, 35(11): 115008. doi: 10.1088/1674-4926/35/11/115008
H B Chen, J X Xiang, X Y Xue, C X Chen, F Ye, J Xu, J Y Ren. An analog front end with a 12-bit 3.2-MS/s SAR ADC for a power line communication system[J]. J. Semicond., 2014, 35(11): 115008. doi: 10.1088/1674-4926/35/11/115008.
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An analog front end with a 12-bit 3.2-MS/s SAR ADC for a power line communication system
doi: 10.1088/1674-4926/35/11/115008
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Abstract
This paper presents an analog front end for a power line communication system, including a 12-bit 3.2-MS/s energy-efficient successive approximation register analog-to-digital converter, a positive feedback programmable gain amplifier, a 9.8 ppm/℃ bandgap reference and on-chip low-output voltage regulators. A two segment capacitive array structure (6 MSB 5 LSB) composed by split capacitors is designed for the SAR core to save area cost and release reference voltage accuracy requirements. Implemented in the GSMC 0.13 μm 1.5 V/12 V dual-gate 4P6M e-flash process, the analog front end occupies an area of 0.457 mm2 and consumes power of 18.8 mW, in which 1.1 mW cost by the SAR ADC. Measured at 500 kHz input, the spurious-free dynamic range and signal-to-noise plus distortion ratio of the ADC are 71.57 dB and 60.60 dB respectively, achieving a figure of merit of 350 fJ/conversion-step. -
References
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