Fig. 1.
Simplified block diagram of the targeted 60 GHz transceiver.
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| Citation: |
Lixue Kuang, Baoyong Chi, Lei Chen, Wen Jia, Zhihua Wang. A fully-differential phase-locked loop frequency synthesizer for 60-GHz wireless communication[J]. Journal of Semiconductors, 2014, 35(12): 125002. doi: 10.1088/1674-4926/35/12/125002
L X Kuang, B Y Chi, L Chen, W Jia, Z H Wang. A fully-differential phase-locked loop frequency synthesizer for 60-GHz wireless communication[J]. J. Semicond., 2014, 35(12): 125002. doi: 10.1088/1674-4926/35/12/125002.
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A fully-differential phase-locked loop frequency synthesizer for 60-GHz wireless communication
doi: 10.1088/1674-4926/35/12/125002
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Abstract
A 40-GHz phase-locked loop (PLL) frequency synthesizer for 60-GHz wireless communication applications is presented. The electrical characteristics of the passive components in the VCO and LO buffers are accurately extracted with an electromagnetic simulator HFSS. A differential tuning technique is utilized in the voltage controlled oscillator (VCO) to achieve higher common-mode noise rejection and better phase noise performance. The VCO and the divider chain are powered by a 1.0 V supply while the phase-frequency detector (PFD) and the charge pump (CP) are powered by a 2.5 V supply to improve the linearity. The measurement results show that the total frequency locking range of the frequency synthesizer is from 37 to 41 GHz, and the phase noise from a 40 GHz carrier is -97.2 dBc/Hz at 1 MHz offset. Implemented in 65 nm CMOS, the synthesizer consumes a DC power of 62 mW, including all the buffers. -
References
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