A PD-SOI based DTI-LOCOS combined cross isolation technique for minimizing TID radiation induced leakage in high density memory

Fengying Qiao; Liyang Pan; Dong Wu; Lifang Liu; Jun Xu

doi:10.1088/1674-4926/35/2/024003

J. Semicond. > 2014, Volume 35 > Issue 2 > 024003, doi: 10.1088/1674-4926/35/2/024003

SEMICONDUCTOR DEVICES

A PD-SOI based DTI-LOCOS combined cross isolation technique for minimizing TID radiation induced leakage in high density memory

Fengying Qiao^1,, Liyang Pan^{1, 2}, Dong Wu^{1, 2}, Lifang Liu¹ and Jun Xu^{1, 2}

+ Author Affiliations

Corresponding author: Qiao Fengying, qfy08@mails.tsinghua.edu.cn

Abstract: In order to minimize leakage current increase under total ionizing dose (TID) radiation in high density memory circuits, a new isolation technique, combining deep trench isolation (DTI) between the wells, local oxidation of silicon (LOCOS) isolation between the devices within the well, and a P-diffused area in order to limit leakage at the isolation edge is implemented in partly-depleted silicon-on-insulator (PD-SOI) technology. This radiation hardening technique can minimize the layout area by more than 60%, and allows flexible placement of the body contact. Radiation hardened transistors and 256 Kb flash memory chips are designed and fabricated in a 0.6 μm PD-SOI process. Experiments show that no obvious increase in leakage current is observed for single transistors under 1 Mrad(Si) radiation, and that the 256 Kb memory chip still functions well after a TID of 100 krad(Si), with only 50% increase of the active power consumption in read mode.

Key words: total ionizing dose, isolation leakage, flash memory, silicon on insulator

References

[1]	Gerardin S, Paccagnella A. Present and future non-volatile memories for space. IEEE Trans Nucl Sci, 2010, 57:3016 http://ieeexplore.ieee.org/document/5658042/?reload=true&tp=&arnumber=5658042&contentType=Journals%20%26%20Magazines&punumber%3D23
[2]	Barnaby H J. Total-ionizing-dose effects in modern CMOS technologies. IEEE Trans Nucl Sci, 2006, 53:3103 doi: 10.1109/TNS.2006.885952
[3]	Dodd P E, Shaneyfelt M R, Schwank J R, et al. Current and future challenges in radiation effects on CMOS electronics. IEEE Trans Nucl Sci, 2010, 57:1747 doi: 10.1109/TNS.2010.2042613
[4]	Ding L L, Guo H X, Chen W, et al. Study of radiation-induced leakage current between adjacent devices in a CMOS integrated circuit. Journal of Semiconductors, 2012, 33(6):064006 doi: 10.1088/1674-4926/33/6/064006
[5]	Qiao F Y, Yu X, Pan L Y, et al. TID characterization of 0. 13μm SONOS cell in 4Mb NOR flash memory. IEEE 19th Symposium on Physical and Failure Analysis of Integrated Circuits, Singapore, 2012: 1
[6]	Bagatin M, Cellere G, Gerardin S, et al. TID sensitivity of NAND flash memory building blocks. IEEE Trans Nucl Sci, 2009, 56:1909 doi: 10.1109/TNS.2009.2016095
[7]	Lacoe R C. Improving integrated circuit performance through the application of hardness-by-design methodology. IEEE Trans Nucl Sci, 2008, 55:1903 doi: 10.1109/TNS.2008.2000480
[8]	Alexander D R. Design issues for radiation tolerant micro circuits for space. IEEE Nuclear and Radiation Effects Conf, Short Course, 1996 http://www.sciencedirect.com/science/article/pii/S0168900299008992
[9]	Schwank J R, Ferlet-Cavrois V, Shaneyfelt M R, et al. Radiation effects in SOI technologies. IEEE Trans Nucl Sci, 2003, 50:522 doi: 10.1109/TNS.2003.812930
[10]	Han X W, Wu L H, Zhao Y, et al. A radiation hardened SOI based FPGA. Journal of Semiconductors, 2011, 32(7):075012 doi: 10.1088/1674-4926/32/7/075012
[11]	Schwank, J R, Albuquerque N M, Shaneyfelt M R, et al. Radiation effects in MOS oxides. IEEE Trans Nucl Sci, 2008, 55:1833 doi: 10.1109/TNS.2008.2001040
[12]	Schrimpf R D, Alles M L, Fleetwood D M, et al. Design and evaluation of SOI devices for radiation environments. IEEE International SOI Conference, 2010:1 http://ieeexplore.ieee.org/document/5641470/
[13]	Nguyen D N, Farokh I. Comparison of TID response of micron technology single-level cell high density NAND flash memories. IEEE Radiation Effects Data Workshop (REDW), Denver, 2010:1 http://ieeexplore.ieee.org/document/5658037/

Fig. 1. Illustration of radiation induced leakage paths in standard CMOS technology.

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Fig. 2. The proposed radiation hardened technique. (a) Layout illustration of PD-SOI based DTI-LOCOS cross isolation technique. (b) Cross section of the radiation harden technique along $aa'$ direction in Fig. 2(a). (c) Cross section of the radiation hardening technique along $bb'$ direction in Fig. 2(a).

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Fig. 3. (a) Schematic of a typical BL data buffer for the memory circuit. (b) Layout of the schematic shown in (a) with method proposed in our paper. (c)--(e) Layout of 4 data buffer circuit modules adjusted with cell pitches with (c) method proposed in this paper in 0.6 $\mu $m PD-SOI technology. (d) ELT and Pplus guard ring isolation technique in 0.6 $\mu $m bulk silicon technology. (e) ELT and DTI all-dielectric isolation technique in 0.6 $\mu $m PD-SOI technology.

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Fig. 4. SEM image of the isolation technique proposed in this paper. (a) DTI-LOCOS combined isolation. (b) DTI in the memory array.

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Fig. 5. (a) The chip photo of the 256 Kb EEPROM fabricated using our radiation hardening techniques. (b) Typical layout of the high density circuit. (c) Typical layout of the memory array.

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Fig. 6. $I_{\rm D}$--$V_{\rm G}$ curves before and after irradiation for NMOS transistors and memory cells. (a) NMOS using the technique proposed in this paper. (b) Standard NMOS transistor. (c) Memory cells in programmed state. (d) Memory cells in erased state.

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Fig. 7. Power supply current of six 256 Kb EEPROM samples before or after irradiation under read mode.

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Table 1. The layout area of three different radiation hardening techniques.

[1]	Gerardin S, Paccagnella A. Present and future non-volatile memories for space. IEEE Trans Nucl Sci, 2010, 57:3016 http://ieeexplore.ieee.org/document/5658042/?reload=true&tp=&arnumber=5658042&contentType=Journals%20%26%20Magazines&punumber%3D23
[2]	Barnaby H J. Total-ionizing-dose effects in modern CMOS technologies. IEEE Trans Nucl Sci, 2006, 53:3103 doi: 10.1109/TNS.2006.885952
[3]	Dodd P E, Shaneyfelt M R, Schwank J R, et al. Current and future challenges in radiation effects on CMOS electronics. IEEE Trans Nucl Sci, 2010, 57:1747 doi: 10.1109/TNS.2010.2042613
[4]	Ding L L, Guo H X, Chen W, et al. Study of radiation-induced leakage current between adjacent devices in a CMOS integrated circuit. Journal of Semiconductors, 2012, 33(6):064006 doi: 10.1088/1674-4926/33/6/064006
[5]	Qiao F Y, Yu X, Pan L Y, et al. TID characterization of 0. 13μm SONOS cell in 4Mb NOR flash memory. IEEE 19th Symposium on Physical and Failure Analysis of Integrated Circuits, Singapore, 2012: 1
[6]	Bagatin M, Cellere G, Gerardin S, et al. TID sensitivity of NAND flash memory building blocks. IEEE Trans Nucl Sci, 2009, 56:1909 doi: 10.1109/TNS.2009.2016095
[7]	Lacoe R C. Improving integrated circuit performance through the application of hardness-by-design methodology. IEEE Trans Nucl Sci, 2008, 55:1903 doi: 10.1109/TNS.2008.2000480
[8]	Alexander D R. Design issues for radiation tolerant micro circuits for space. IEEE Nuclear and Radiation Effects Conf, Short Course, 1996 http://www.sciencedirect.com/science/article/pii/S0168900299008992
[9]	Schwank J R, Ferlet-Cavrois V, Shaneyfelt M R, et al. Radiation effects in SOI technologies. IEEE Trans Nucl Sci, 2003, 50:522 doi: 10.1109/TNS.2003.812930
[10]	Han X W, Wu L H, Zhao Y, et al. A radiation hardened SOI based FPGA. Journal of Semiconductors, 2011, 32(7):075012 doi: 10.1088/1674-4926/32/7/075012
[11]	Schwank, J R, Albuquerque N M, Shaneyfelt M R, et al. Radiation effects in MOS oxides. IEEE Trans Nucl Sci, 2008, 55:1833 doi: 10.1109/TNS.2008.2001040
[12]	Schrimpf R D, Alles M L, Fleetwood D M, et al. Design and evaluation of SOI devices for radiation environments. IEEE International SOI Conference, 2010:1 http://ieeexplore.ieee.org/document/5641470/
[13]	Nguyen D N, Farokh I. Comparison of TID response of micron technology single-level cell high density NAND flash memories. IEEE Radiation Effects Data Workshop (REDW), Denver, 2010:1 http://ieeexplore.ieee.org/document/5658037/

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Received: 17 July 2013 Revised: 03 September 2013 Online: Published: 01 February 2014

Article Navigation > Journal of Semiconductors > 2014 > 35(2): 024003

Fengying Qiao, Liyang Pan, Dong Wu, Lifang Liu, Jun Xu. A PD-SOI based DTI-LOCOS combined cross isolation technique for minimizing TID radiation induced leakage in high density memory[J]. Journal of Semiconductors, 2014, 35(2): 024003. doi: 10.1088/1674-4926/35/2/024003 F Y Qiao, L Y Pan, D Wu, L F Liu, J Xu. A PD-SOI based DTI-LOCOS combined cross isolation technique for minimizing TID radiation induced leakage in high density memory[J]. J. Semicond., 2014, 35(2): 024003. doi: 10.1088/1674-4926/35/2/024003.Export: BibTex EndNote

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F Y Qiao, L Y Pan, D Wu, L F Liu, J Xu. A PD-SOI based DTI-LOCOS combined cross isolation technique for minimizing TID radiation induced leakage in high density memory[J]. J. Semicond., 2014, 35(2): 024003. doi: 10.1088/1674-4926/35/2/024003.

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A PD-SOI based DTI-LOCOS combined cross isolation technique for minimizing TID radiation induced leakage in high density memory

doi: 10.1088/1674-4926/35/2/024003

1.
Institute of Microelectronics, Tsinghua University, Beijing 100084, China
2.
Tsinghua National Laboratory for Information Science and Technology, Beijing 100084, China

Funds:

the National Natural Science Foundation of China 61176033

the National Key Basic Research Program 2011CBA00602

Project supported by the National Key Basic Research Program (No. 2011CBA00602) and the National Natural Science Foundation of China (Nos. 61106102, 61176033)

the National Natural Science Foundation of China 61106102

More Information

Corresponding author: Qiao Fengying, qfy08@mails.tsinghua.edu.cn
Received Date: 2013-07-17
Revised Date: 2013-09-03
Published Date: 2014-02-01

Abstract

Abstract

In order to minimize leakage current increase under total ionizing dose (TID) radiation in high density memory circuits, a new isolation technique, combining deep trench isolation (DTI) between the wells, local oxidation of silicon (LOCOS) isolation between the devices within the well, and a P-diffused area in order to limit leakage at the isolation edge is implemented in partly-depleted silicon-on-insulator (PD-SOI) technology. This radiation hardening technique can minimize the layout area by more than 60%, and allows flexible placement of the body contact. Radiation hardened transistors and 256 Kb flash memory chips are designed and fabricated in a 0.6 μm PD-SOI process. Experiments show that no obvious increase in leakage current is observed for single transistors under 1 Mrad(Si) radiation, and that the 256 Kb memory chip still functions well after a TID of 100 krad(Si), with only 50% increase of the active power consumption in read mode.
- total ionizing dose,
- isolation leakage,
- flash memory,
- silicon on insulator

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References(13)

References

[1]	Gerardin S, Paccagnella A. Present and future non-volatile memories for space. IEEE Trans Nucl Sci, 2010, 57:3016 http://ieeexplore.ieee.org/document/5658042/?reload=true&tp=&arnumber=5658042&contentType=Journals%20%26%20Magazines&punumber%3D23
[2]	Barnaby H J. Total-ionizing-dose effects in modern CMOS technologies. IEEE Trans Nucl Sci, 2006, 53:3103 doi: 10.1109/TNS.2006.885952
[3]	Dodd P E, Shaneyfelt M R, Schwank J R, et al. Current and future challenges in radiation effects on CMOS electronics. IEEE Trans Nucl Sci, 2010, 57:1747 doi: 10.1109/TNS.2010.2042613
[4]	Ding L L, Guo H X, Chen W, et al. Study of radiation-induced leakage current between adjacent devices in a CMOS integrated circuit. Journal of Semiconductors, 2012, 33(6):064006 doi: 10.1088/1674-4926/33/6/064006
[5]	Qiao F Y, Yu X, Pan L Y, et al. TID characterization of 0. 13μm SONOS cell in 4Mb NOR flash memory. IEEE 19th Symposium on Physical and Failure Analysis of Integrated Circuits, Singapore, 2012: 1
[6]	Bagatin M, Cellere G, Gerardin S, et al. TID sensitivity of NAND flash memory building blocks. IEEE Trans Nucl Sci, 2009, 56:1909 doi: 10.1109/TNS.2009.2016095
[7]	Lacoe R C. Improving integrated circuit performance through the application of hardness-by-design methodology. IEEE Trans Nucl Sci, 2008, 55:1903 doi: 10.1109/TNS.2008.2000480
[8]	Alexander D R. Design issues for radiation tolerant micro circuits for space. IEEE Nuclear and Radiation Effects Conf, Short Course, 1996 http://www.sciencedirect.com/science/article/pii/S0168900299008992
[9]	Schwank J R, Ferlet-Cavrois V, Shaneyfelt M R, et al. Radiation effects in SOI technologies. IEEE Trans Nucl Sci, 2003, 50:522 doi: 10.1109/TNS.2003.812930
[10]	Han X W, Wu L H, Zhao Y, et al. A radiation hardened SOI based FPGA. Journal of Semiconductors, 2011, 32(7):075012 doi: 10.1088/1674-4926/32/7/075012
[11]	Schwank, J R, Albuquerque N M, Shaneyfelt M R, et al. Radiation effects in MOS oxides. IEEE Trans Nucl Sci, 2008, 55:1833 doi: 10.1109/TNS.2008.2001040
[12]	Schrimpf R D, Alles M L, Fleetwood D M, et al. Design and evaluation of SOI devices for radiation environments. IEEE International SOI Conference, 2010:1 http://ieeexplore.ieee.org/document/5641470/
[13]	Nguyen D N, Farokh I. Comparison of TID response of micron technology single-level cell high density NAND flash memories. IEEE Radiation Effects Data Workshop (REDW), Denver, 2010:1 http://ieeexplore.ieee.org/document/5658037/

A PD-SOI based DTI-LOCOS combined cross isolation technique for minimizing TID radiation induced leakage in high density memory

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