SEMICONDUCTOR INTEGRATED CIRCUITS

An effective timing characterization method for an accuracy-proved VLSI standard cell library

Jianhua Jiang, Man Liang, Lei Wang and Yumei Zhou

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 Corresponding author: Jiang Jianhua, Email:jiangjianhua@ime.ac.cn

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Abstract: This paper presents a method of tailoring the characterization and modeling timing of a VLSI standard cell library. The paper also presents a method to validate the reasonability of the value through accuracy analysis. In the process of designing a standard cell library, this method is applied to characterize the cell library. In addition, the error calculations of some simple circuit path delays are compared between using the characterization file and an Hspice simulation. The comparison results demonstrate the accuracy of the generated timing library file.

Key words: characteristic parameterserror calculationlook-up tableLib file



[1]
Zhang K, Wang D H, Li Y G. Library building for sub-micron CMOS process. Fifth International IEEE Conference on ASIC, 2003:1369
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Library CompilerTM Modeling Timing, Signal Integrity, and Power in Technology Libraries User Guide
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Scheffer L. EDA for IC implementation, circuit design, and process technology. Addision-Wesley, Reading
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Gao Mingzhi, Ye Zuochang, Wang Yan, et al, On modeling the digital gate delay under process variation. Journal of Semiconductors, 2011, 32(7):075010 doi: 10.1088/1674-4926/32/7/075010
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Miryala S, Kaur B, Anand B, et al. Efficient nanoscale VLSI standard cell library characterization using a novel delay model. 12th Int'l Symposium on Quality Electronic Design, 2011 http://ieeexplore.ieee.org/document/5770767/keywords
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LibertyTM NCX User Guide Version B, December 2008
Fig. 1.  An example cell delay arc

Fig. 2.  NLDM calculation schematic

Fig. 3.  Coordinate for linear interpolation

Fig. 4.  Variation of characteristic values with output load capacitance ($C_{\rm l})$. (a) Cell fall. (b) Cell rise. (c) Rise transition. (d) Fall transition

Fig. 5.  Variation of characteristic values with input transition time ($C_{\rm l})$. (a) Cell fall. (b) Cell rise. (c) Rise transition. (d) Fall transition

Fig. 6.  Logarithmic distribution histogram

Fig. 7.  Uniform distribution histogram

Fig. 8.  Normal distribution histogram

Fig. 9.  Schematic of C17

Fig. 10.  Layout of C17

Table 1.   Coefficient values for fall cell delay

Table 2.   Correspondence value of MCy and yield

Table 3.   Correspondence value of MCy and yield

[1]
Zhang K, Wang D H, Li Y G. Library building for sub-micron CMOS process. Fifth International IEEE Conference on ASIC, 2003:1369
[2]
Library CompilerTM Modeling Timing, Signal Integrity, and Power in Technology Libraries User Guide
[3]
Scheffer L. EDA for IC implementation, circuit design, and process technology. Addision-Wesley, Reading
[4]
Gao Mingzhi, Ye Zuochang, Wang Yan, et al, On modeling the digital gate delay under process variation. Journal of Semiconductors, 2011, 32(7):075010 doi: 10.1088/1674-4926/32/7/075010
[5]
Ackalloor B, Gaitonde D. An overview of library characterization in semi-custom design. IEEE Custom Integrated Circuits Conference, 1998
[6]
Rachit I K, Bhat M S. AutoLibGen:an open source tool for standard cell library characterization at 65nm technology. International Conference on Electronic Design Penang, Malaysia, 2008 http://ieeexplore.ieee.org/document/4786726/authors
[7]
Miryala S, Kaur B, Anand B, et al. Efficient nanoscale VLSI standard cell library characterization using a novel delay model. 12th Int'l Symposium on Quality Electronic Design, 2011 http://ieeexplore.ieee.org/document/5770767/keywords
[8]
LibertyTM NCX User Guide Version B, December 2008
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    Received: 05 July 2013 Revised: 28 August 2013 Online: Published: 01 February 2014

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      Jianhua Jiang, Man Liang, Lei Wang, Yumei Zhou. An effective timing characterization method for an accuracy-proved VLSI standard cell library[J]. Journal of Semiconductors, 2014, 35(2): 025005. doi: 10.1088/1674-4926/35/2/025005 J H Jiang, M Liang, L Wang, Y M Zhou. An effective timing characterization method for an accuracy-proved VLSI standard cell library[J]. J. Semicond., 2014, 35(2): 025005. doi: 10.1088/1674-4926/35/2/025005.Export: BibTex EndNote
      Citation:
      Jianhua Jiang, Man Liang, Lei Wang, Yumei Zhou. An effective timing characterization method for an accuracy-proved VLSI standard cell library[J]. Journal of Semiconductors, 2014, 35(2): 025005. doi: 10.1088/1674-4926/35/2/025005

      J H Jiang, M Liang, L Wang, Y M Zhou. An effective timing characterization method for an accuracy-proved VLSI standard cell library[J]. J. Semicond., 2014, 35(2): 025005. doi: 10.1088/1674-4926/35/2/025005.
      Export: BibTex EndNote

      An effective timing characterization method for an accuracy-proved VLSI standard cell library

      doi: 10.1088/1674-4926/35/2/025005
      Funds:

      Project supported by the National Science and Technology Major Project (No. 10ZX02305-013-002/10ZX02305-013-004)

      the National Science and Technology Major Project 10ZX02305-013-002

      the National Science and Technology Major Project 10ZX02305-013-004

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      • Corresponding author: Jiang Jianhua, Email:jiangjianhua@ime.ac.cn
      • Received Date: 2013-07-05
      • Revised Date: 2013-08-28
      • Published Date: 2014-02-01

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