J. Semicond. > 2014, Volume 35 > Issue 3 > 034008, doi: 10.1088/1674-4926/35/3/034008
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SEMICONDUCTOR DEVICES

The STI stress effect on deep submicron PDSOI MOSFETs

Jianhui Bu, Shuzhen Li, Jiajun Luo and Zhengsheng Han

+ Author Affiliations

 Corresponding author: Bu Jianhui, Email:bujianhui@ime.ac.cn

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Abstract: The STI stress effect is investigated based on the 0.13 μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS). It shows that the threshold voltage and mobility are all affected by the STI stress. The absolute value of the threshold voltage of NMOS and PMOS increased by about 10%, the saturation current of NMOS decreases by about 20%, while the saturation current of PMOS increases by about 20%. It is also found that the lower temperature enhances the STI stress and then influences the device performance further. Then a macro model for this effect is proposed and is well verified.

Key words: PDSOI, STI stress, temperature, model



[1]
Tan P B Y, Kordesch A V, Sidek O. Compact modeling of mechanical STI y-stress effect. IEEE International Conference on Solid-State and Integrated Circuit Technology, 2006:1450 http://ieeexplore.ieee.org/document/4098437/
[2]
Tan P B Y, Kordesch A V, Sidek O. Physical-based SPICE model of CMOS STI y-stress effect. IEEE International Conference on Semiconductor Electronics, 2006:755 http://ieeexplore.ieee.org/document/4266720/
[3]
Yeh K L, Guo J C. Layout-dependent stress effect on high-frequency characteristics and flicker noise in multifinger and donut MOSFETs. IEEE Trans Electron Devices, 2011, 58(9):3140 doi: 10.1109/TED.2011.2159223
[4]
Wu W, Du G, Liu X, et al. Physical-based threshold voltage and mobility models including shallow trench isolation stress effect on nMOSFETs. IEEE Trans Nanotechnology, 2011, 10(4):875 doi: 10.1109/TNANO.2010.2089468
[5]
Wu Wei, Du Gang, Liu Xiaoyan, et al. A physical-based pMOSFETs threshold voltage model including the STI stress effect. Journal of smiconductors, 2011, 32(5):054005 doi: 10.1088/1674-4926/32/5/054005
[6]
Jiang H, Yap H K, Pandey S M, et al. Impact of STI stress on hot carrier degradation in 5 V NMOSFET. IEEE International Integrated Reliability Workshop Final Report (IRW), 2011:94
[7]
BSIMSOIv4. 4 MOSFET MODEL Users' Manual. 2010: 54
[8]
Tan P B Y, Kordesch A V, Sidek O. Analysis of deep submicron CMOS transistor Vtlin and Idsat versus channel width. Asia-Pacific Microwave Conference (APMC), 2005:1569
Fig. 1.  The simplified layout of the MOSFETs.

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Fig. 2.  The transfer curve of the MOSFETs with different SA ($W=$ 2 $\mu $m, $L=$ 0.13 $\mu $m). (a) NMOS. (b) PMOS.

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Fig. 3.  The output curve of the MOSFETs with different SA ($W=$ 2 $\mu $m, $L=$ 0.13 $\mu $m). (a) NMOS. (b) PMOS.

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Fig. 4.  The influence of the STI stress on $V_{\rm th}$ at different temperatures ($W=$ 2 $\mu $m, $L=$ 0.13 $\mu $m). (a) NMOS. (b) PMOS.

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Fig. 5.  The influence of the STI stress on $I_{\rm dlin}$ at different temperatures ($W=$ 2 $\mu $m, $L=$ 0.13 $\mu $m). (a) NMOS. (b) PMOS.

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Fig. 6.  The measured $I_{\rm dlin}$ and simulated $I_{\rm dlin}$ curve.

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[1]
Tan P B Y, Kordesch A V, Sidek O. Compact modeling of mechanical STI y-stress effect. IEEE International Conference on Solid-State and Integrated Circuit Technology, 2006:1450 http://ieeexplore.ieee.org/document/4098437/
[2]
Tan P B Y, Kordesch A V, Sidek O. Physical-based SPICE model of CMOS STI y-stress effect. IEEE International Conference on Semiconductor Electronics, 2006:755 http://ieeexplore.ieee.org/document/4266720/
[3]
Yeh K L, Guo J C. Layout-dependent stress effect on high-frequency characteristics and flicker noise in multifinger and donut MOSFETs. IEEE Trans Electron Devices, 2011, 58(9):3140 doi: 10.1109/TED.2011.2159223
[4]
Wu W, Du G, Liu X, et al. Physical-based threshold voltage and mobility models including shallow trench isolation stress effect on nMOSFETs. IEEE Trans Nanotechnology, 2011, 10(4):875 doi: 10.1109/TNANO.2010.2089468
[5]
Wu Wei, Du Gang, Liu Xiaoyan, et al. A physical-based pMOSFETs threshold voltage model including the STI stress effect. Journal of smiconductors, 2011, 32(5):054005 doi: 10.1088/1674-4926/32/5/054005
[6]
Jiang H, Yap H K, Pandey S M, et al. Impact of STI stress on hot carrier degradation in 5 V NMOSFET. IEEE International Integrated Reliability Workshop Final Report (IRW), 2011:94
[7]
BSIMSOIv4. 4 MOSFET MODEL Users' Manual. 2010: 54
[8]
Tan P B Y, Kordesch A V, Sidek O. Analysis of deep submicron CMOS transistor Vtlin and Idsat versus channel width. Asia-Pacific Microwave Conference (APMC), 2005:1569

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    Received: 11 August 2013 Revised: 09 October 2013 Online: Published: 01 March 2014

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      Article Navigation >  Journal of Semiconductors  > 2014  >  35(3): 034008
      Jianhui Bu, Shuzhen Li, Jiajun Luo, Zhengsheng Han. The STI stress effect on deep submicron PDSOI MOSFETs[J]. Journal of Semiconductors, 2014, 35(3): 034008. doi: 10.1088/1674-4926/35/3/034008 J H Bu, S Z Li, J J Luo, Z S Han. The STI stress effect on deep submicron PDSOI MOSFETs[J]. J. Semicond., 2014, 35(3): 034008. doi: 10.1088/1674-4926/35/3/034008.Export: BibTex EndNote
      Citation:
      Jianhui Bu, Shuzhen Li, Jiajun Luo, Zhengsheng Han. The STI stress effect on deep submicron PDSOI MOSFETs[J]. Journal of Semiconductors, 2014, 35(3): 034008. doi: 10.1088/1674-4926/35/3/034008

      J H Bu, S Z Li, J J Luo, Z S Han. The STI stress effect on deep submicron PDSOI MOSFETs[J]. J. Semicond., 2014, 35(3): 034008. doi: 10.1088/1674-4926/35/3/034008.
      Export: BibTex EndNote
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      The STI stress effect on deep submicron PDSOI MOSFETs

      doi: 10.1088/1674-4926/35/3/034008

      • Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

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      • Corresponding author: Bu Jianhui, Email:bujianhui@ime.ac.cn
      • Received Date: 2013-08-11
      • Revised Date: 2013-10-09
      • Published Date: 2014-03-01

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