Fig. 1.
Proposed PGA with (a) resistor network, (b) closed-loop gain control stage, (c) variable input and load transconductance and (d) variable input transconductance.
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| Citation: |
Nan Lin, Fei Fang, Zhiliang Hong, Hao Fang. A 3.8 GHz programmable gain amplifier with a 0.1 dB gain step[J]. Journal of Semiconductors, 2014, 35(3): 035004. doi: 10.1088/1674-4926/35/3/035004
N Lin, F Fang, Z L Hong, H Fang. A 3.8 GHz programmable gain amplifier with a 0.1 dB gain step[J]. J. Semicond., 2014, 35(3): 035004. doi: 10.1088/1674-4926/35/3/035004.
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A 3.8 GHz programmable gain amplifier with a 0.1 dB gain step
doi: 10.1088/1674-4926/35/3/035004
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Abstract
A broadband programmable gain amplifier (PGA) with a small gain step and low gain error has been designed in 0.13 μm CMOS technology. The PGA was implemented with open-loop architecture to provide wide bandwidth. A two-stage gain control method, which consists of a resistor ladder attenuator and an active fine gain control stage, provides the small gain step. A look-up table based gain control method is introduced in the fine gain control stage to lower the gain error. The proposed PGA shows a decibel-linear variable gain from -4 to 20 dB with a gain step of 0.1 dB and a gain error less than ±0.05 dB. The 3-dB bandwidth and maximum ⅡP3 are 3.8 GHz and 17 dBm, respectively. -
References
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