Fig. 1.
Block diagram of the designed 6-bit pseudo-thermometer segmented DAC.
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| Citation: |
Yijun Song, Wenyuan Li. A 6-bit 4 GS/s pseudo-thermometer segmented CMOS DAC[J]. Journal of Semiconductors, 2014, 35(6): 065007. doi: 10.1088/1674-4926/35/6/065007
Y J Song, W Y Li. A 6-bit 4 GS/s pseudo-thermometer segmented CMOS DAC[J]. J. Semicond., 2014, 35(6): 065007. doi: 10.1088/1674-4926/35/6/065007.
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A 6-bit 4 GS/s pseudo-thermometer segmented CMOS DAC
doi: 10.1088/1674-4926/35/6/065007
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Abstract
A 6-bit 4 GS/s, high-speed and power-efficient DAC for ultra-high-speed transceivers in 60 GHz band millimeter wave technology is presented. A novel pseudo-thermometer architecture is proposed to realize a good compromise between the fast conversion speed and the chip area. Symmetrical and compact floor planning and layout techniques including tree-like routing, cross-quading and common-centroid method are adopted to guarantee the chip is fully functional up to near-Nyquist frequency in a standard 0.18 μm CMOS process. Post simulation results corroborate the feasibility of the designed DAC, which can perform good static and dynamic linearity without calibration. DNL errors and INL errors can be controlled within ±0.28 LSB and ±0.26 LSB, respectively. SFDR at 4 GHz clock frequency for a 1.9 GHz near-Nyquist sinusoidal output signal is 40.83 dB and the power dissipation is less than 37 mW.-
Keywords:
- high speed DAC,
- CMOS,
- current-steering,
- near-Nyquist sampling
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References
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