Fig. 1.
Basic 4-transistors CMOS image pixel configuration.
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Chen Cao, Bing Zhang, Longsheng Wu, Xin Li, Junfeng Wang. Pinch-off voltage modeling for CMOS image pixels with a pinned photodiode structure[J]. Journal of Semiconductors, 2014, 35(7): 074012. doi: 10.1088/1674-4926/35/7/074012
C Cao, B Zhang, L S Wu, X Li, J F Wang. Pinch-off voltage modeling for CMOS image pixels with a pinned photodiode structure[J]. J. Semicond., 2014, 35(7): 074012. doi: 10.1088/1674-4926/35/7/074012.
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Pinch-off voltage modeling for CMOS image pixels with a pinned photodiode structure
doi: 10.1088/1674-4926/35/7/074012
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Abstract
A novel analytical model of pinch-off voltage for CMOS image pixels with a pinned photodiode structure is proposed. The derived model takes account of the gradient doping distributions in the N buried layer due to the impurity compensation formed by manufacturing processes; the impurity distribution characteristics of two boundary PN junctions located in the region for particular spectrum response of a pinned photodiode are quantitative analyzed. By solving Poisson's equation in vertical barrier regions, the relationships between the pinch-off voltage and the corresponding process parameters such as peak doping concentration, N type width and doping concentration gradient of the N buried layer are established. Test results have shown that the derived model features the variations of the pinch-off voltage versus the process implant conditions more accurately than the traditional model. The research conclusions in this paper provide theoretical evidence for evaluating the pinch-off voltage design.-
Keywords:
- pinned photodiode,
- pixel design,
- pinch-off voltage,
- analytical model
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References
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