J. Semicond. > 2014, Volume 35 > Issue 9 > 095001, doi: 10.1088/1674-4926/35/9/095001
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SEMICONDUCTOR INTEGRATED CIRCUITS

Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator

Jitendra Kanungo1, and S. Dasgupta2

+ Author Affiliations

 Corresponding author: Jitendra Kanungo, Email:jitendra.kanungo@juet.ac.in

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Abstract: We analyze the energy performance of a complete adiabatic circuit/system including the Power Clock Generator (PCG) at the 90 nm CMOS technology node. The energy performance in terms of the conversion efficiency of the PCG is extensively carried out under the variations of supply voltage, process corner and the driver transistor's width. We propose an energy-efficient singe cycle control circuit based on the two-stage comparator for the synchronous charge recovery sinusoidal power clock generator (PCG). The proposed PCG is used to drive the 4-bit adiabatic Ripple Carry Adder (RCA) and their simulation results are compared with the adiabatic RCA driven by the reported PCG. We have also simulated the logically equivalent static CMOS RCA circuit to compare the energy saving of adiabatic and non-adiabatic logic circuits. In the clock frequency range from 25 MHz to 1GHz, the proposed PCG gives a maximum conversion efficiency of 56.48%. This research work shows how the design of an efficient PCG increases the energy saving of adiabatic logic.

Key words: clock-generator, energy recovery logic, low power, single phase sinusoidal clock



[1]
Dikinson A G, Denkar J S. Adiabatic dynamic logic. IEEE J Solid-State Circuits, 1995, 30(3):311 doi: 10.1109/4.364447
[2]
Mahmoodi-Meimand H, Afzali-Kusha A. Efficient power clock generation for adiabatic logic. Proc IEEE Int Symposium on Circuits and Systems (ISCAS), 2001, 4:642
[3]
Athas W C, Svensson L J, Tzartzanis N. A resonant signal driver for two-phase, almost-non-overlapping clocks. Proceedings of the International Symposium on Circuits and Systems, 1996:12
[4]
Maksimovic D, Oklobdzija V G. Integrated power clock generators for low energy logic. Proceedings of IEEE Power Electronics Specialists Conference, 1995:61
[5]
Nayan A N, Takahashi Y, Sekine T. LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier. Microelectron J, 2012, 43(4):244 doi: 10.1016/j.mejo.2011.12.013
[6]
Moon Y, Jeong D K. A 32×32-b adiabatic register file with supply clock generator. IEEE J Solid-State Circuits, 1998, 33(5):696 doi: 10.1109/4.668983
[7]
Arsalan M, Shams M. Charge-recovery power clock generators for adiabatic logic circuits. Proc 18th International Conference on VLSI Design, 2005:171
[8]
Maksimovic D, Oklobdzija V G, Nikolic B, et al. Clocked CMOS adiabatic logic with integrated single-phase power-clock supply. IEEE Trans Very Large Scale Integration (VLSI) Systems, 2000, 8(4):460 doi: 10.1109/92.863629
[9]
Marjonen J, Aberg M. A single phase clocked adiabatic static logic-a proposal for digital low power applications. Kluwer Academic Pub J of VLSI Signal Processing, 2001, 27:253 doi: 10.1023/A:1008143316204
[10]
Maksimovic D, Oklobdzija V G. Integrated power clock generators for low energy logic. Proc 26th IEEE Annual Conf on Power Electronics Specialists (PESC), 1995, 1:61 doi: 10.1109/PESC.1995.474793
[11]
Bargagli-Stoffi, Iannaccone G, Pascoli S D, et al. Four-phase power clock generator for adiabatic logic circuits. IEE Electron Lett, 2002, 38(14):689 doi: 10.1049/el:20020523
[12]
Ziesier C H, Kim S, Papaefthymiou M C. A resonant clock generator for single-phase adiabatic systems. Proc IEEE Int Symposium on Low Power Electronics and Design, 2001:159
[13]
Svensson L J, Koller J G. Driving a capacitive load without dissipating fCV2. Proc IEEE Symposium on Low Power Electronics, Digest of Technical Papers, 1994:100
[14]
Teichmann P. Adiabatic logic:future trend and system level perspective-first edition. Springer Series in Advanced Microelectronics, 2012
[15]
Fisher J, Teichmann P, Landsiedel M D S. Scaling trends in adiabatic logic. Proc ACM 2nd Conference on Computing Frontiers, 2005:427
[16]
Kanungo J, Dasgupta S. Scaling trends in energy recovery logic:an analytical approach. Journal of Semiconductors, 2013, 34(8):085001 doi: 10.1088/1674-4926/34/8/085001
[17]
Sathe V S, Chueh J Y, Papaefthyymiou M C. Energy-efficient GHz-class charge-recovery logic. IEEE J Solid-State Circuits, 2007, 42(1):38 doi: 10.1109/JSSC.2006.885053
[18]
Ziesler C H, Joohee K, Sathe V S, et al. A 225 MHz resonant clocked ASIC chip. Proc Int Symposium on Low Power Electronics and Design, 2003:48
[19]
Ziesler C H, Joohee K, Papaefthymiou M C. Energy recovering ASIC design. Proc IEEE Computer Society Annual Symposium on VLSI, 2003:133
[20]
Kim S, Ziesler C H, Papaefthyymiou M C. A true-single phase energy-recovery multiplier. IEEE Trans Very Large Scale Integration (VLSI) Systems, 2003, 11(2):194 doi: 10.1109/TVLSI.2003.810795
[21]
Masksimovic D, Oklobdzija V G, Nikolic B, et al. Clocked CMOS adiabatic logic with integrated single-phase power-clock supply. IEEE Trans Very Large Scale Integration (VLSI) Systems, 2000, 8(4):460 doi: 10.1109/92.863629
[22]
Baker R J. CMOS circuit design, layout, and simulation. 3rd ed. IEEE Series on Microelectronics Systems, Wiley, 2010
[23]
Nikolic B, Stojanovic V, Oklobdzija V G, et al. Sense amplifier-based flip-flop. Proc IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 1999:283
[24]
Wicht B, Nirschl T, Schmitt-Landsiedel D. Yield and speed optimization of a latch-type voltage sense amplifier. IEEE J Solid-State Circuits, 2004, 39(7):1148 doi: 10.1109/JSSC.2004.829399
[25]
Goll B, Zimmermann H. A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65 V. IEEE Trans Circuits Syst Ⅱ:Express Briefs, 2009, 56(11):810 doi: 10.1109/TCSII.2009.2030357
[26]
Athas W C, Svensson L J, Koller J G, et al. Low-power digital systems based on adiabatic-switching principles. IEEE Trans Very Large Scale Integration (VLSI) Systems, 1994, 2(4):398 doi: 10.1109/92.335009
[27]
Rabaey J M, Chandrakasan A, Nikolic B. Digital integrated circuits: a design perspective. 2nd ed. Prentice Hall Electronics and VLSI Series, Pearson Education, Singapore: Pte Ltd, 2003
[28]
Montanaro J, Witek R T, Anne K, et al. A 160 MHz 32-b 0.5-W CMOS RISC microprocessor. IEEE J Solid-State Circuits, 1996, 31(11):1703 doi: 10.1109/JSSC.1996.542315
[29]
Mahmoodi H, Tirumalashetty V, Cooke M, et al. Ultra low-power clocking scheme using energy recovery and clock gating. IEEE Trans Very Large Scale Integration (VLSI) Systems, 2009, 17(1):33 doi: 10.1109/TVLSI.2008.2008453
[30]
Mahmoodi-Meinnand H, Afzali-Kusha A, Nourani M. Adiabatic carry look-ahead adder with efficient power clock generator. IEE Proceedings Circuits, Devices and Systems, 2001, 148(5):229 doi: 10.1049/ip-cds:20010439
Fig. 1.  Block diagram of a synchronous resonant power clock generator[7]

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Fig. 2.  (a) Conventional charging of a RC circuit. (b) Adiabatic charging of a RC circuit[1]

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Fig. 3.  Reported synchronous single phase resonant power clock generator for adiabatic logic[18, 19]

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Fig. 4.  Proposed synchronous single phase resonant power clock generator for adiabatic logic

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Fig. 5.  The fundamental adiabatic buffer/inverter[26]

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Fig. 6.  Conversion efficiency versus frequency with process corner variation for the 4-bit adiabatic RCA at 90 nm CMOS technology driven by (a) proposed PCG and (b) reported PCG

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Fig. 7.  Conversion efficiency versus driver transistor width for the 4-bit adiabatic RCA at 90 nm CMOS technology driven by (a) proposed PCG and (b) reported PCG

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Table 1.   Conversion efficiency of PCGs which drive the 4-bit RCA for supply voltage variation at 90 nm CMOS technology node
[1]
Dikinson A G, Denkar J S. Adiabatic dynamic logic. IEEE J Solid-State Circuits, 1995, 30(3):311 doi: 10.1109/4.364447
[2]
Mahmoodi-Meimand H, Afzali-Kusha A. Efficient power clock generation for adiabatic logic. Proc IEEE Int Symposium on Circuits and Systems (ISCAS), 2001, 4:642
[3]
Athas W C, Svensson L J, Tzartzanis N. A resonant signal driver for two-phase, almost-non-overlapping clocks. Proceedings of the International Symposium on Circuits and Systems, 1996:12
[4]
Maksimovic D, Oklobdzija V G. Integrated power clock generators for low energy logic. Proceedings of IEEE Power Electronics Specialists Conference, 1995:61
[5]
Nayan A N, Takahashi Y, Sekine T. LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier. Microelectron J, 2012, 43(4):244 doi: 10.1016/j.mejo.2011.12.013
[6]
Moon Y, Jeong D K. A 32×32-b adiabatic register file with supply clock generator. IEEE J Solid-State Circuits, 1998, 33(5):696 doi: 10.1109/4.668983
[7]
Arsalan M, Shams M. Charge-recovery power clock generators for adiabatic logic circuits. Proc 18th International Conference on VLSI Design, 2005:171
[8]
Maksimovic D, Oklobdzija V G, Nikolic B, et al. Clocked CMOS adiabatic logic with integrated single-phase power-clock supply. IEEE Trans Very Large Scale Integration (VLSI) Systems, 2000, 8(4):460 doi: 10.1109/92.863629
[9]
Marjonen J, Aberg M. A single phase clocked adiabatic static logic-a proposal for digital low power applications. Kluwer Academic Pub J of VLSI Signal Processing, 2001, 27:253 doi: 10.1023/A:1008143316204
[10]
Maksimovic D, Oklobdzija V G. Integrated power clock generators for low energy logic. Proc 26th IEEE Annual Conf on Power Electronics Specialists (PESC), 1995, 1:61 doi: 10.1109/PESC.1995.474793
[11]
Bargagli-Stoffi, Iannaccone G, Pascoli S D, et al. Four-phase power clock generator for adiabatic logic circuits. IEE Electron Lett, 2002, 38(14):689 doi: 10.1049/el:20020523
[12]
Ziesier C H, Kim S, Papaefthymiou M C. A resonant clock generator for single-phase adiabatic systems. Proc IEEE Int Symposium on Low Power Electronics and Design, 2001:159
[13]
Svensson L J, Koller J G. Driving a capacitive load without dissipating fCV2. Proc IEEE Symposium on Low Power Electronics, Digest of Technical Papers, 1994:100
[14]
Teichmann P. Adiabatic logic:future trend and system level perspective-first edition. Springer Series in Advanced Microelectronics, 2012
[15]
Fisher J, Teichmann P, Landsiedel M D S. Scaling trends in adiabatic logic. Proc ACM 2nd Conference on Computing Frontiers, 2005:427
[16]
Kanungo J, Dasgupta S. Scaling trends in energy recovery logic:an analytical approach. Journal of Semiconductors, 2013, 34(8):085001 doi: 10.1088/1674-4926/34/8/085001
[17]
Sathe V S, Chueh J Y, Papaefthyymiou M C. Energy-efficient GHz-class charge-recovery logic. IEEE J Solid-State Circuits, 2007, 42(1):38 doi: 10.1109/JSSC.2006.885053
[18]
Ziesler C H, Joohee K, Sathe V S, et al. A 225 MHz resonant clocked ASIC chip. Proc Int Symposium on Low Power Electronics and Design, 2003:48
[19]
Ziesler C H, Joohee K, Papaefthymiou M C. Energy recovering ASIC design. Proc IEEE Computer Society Annual Symposium on VLSI, 2003:133
[20]
Kim S, Ziesler C H, Papaefthyymiou M C. A true-single phase energy-recovery multiplier. IEEE Trans Very Large Scale Integration (VLSI) Systems, 2003, 11(2):194 doi: 10.1109/TVLSI.2003.810795
[21]
Masksimovic D, Oklobdzija V G, Nikolic B, et al. Clocked CMOS adiabatic logic with integrated single-phase power-clock supply. IEEE Trans Very Large Scale Integration (VLSI) Systems, 2000, 8(4):460 doi: 10.1109/92.863629
[22]
Baker R J. CMOS circuit design, layout, and simulation. 3rd ed. IEEE Series on Microelectronics Systems, Wiley, 2010
[23]
Nikolic B, Stojanovic V, Oklobdzija V G, et al. Sense amplifier-based flip-flop. Proc IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 1999:283
[24]
Wicht B, Nirschl T, Schmitt-Landsiedel D. Yield and speed optimization of a latch-type voltage sense amplifier. IEEE J Solid-State Circuits, 2004, 39(7):1148 doi: 10.1109/JSSC.2004.829399
[25]
Goll B, Zimmermann H. A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65 V. IEEE Trans Circuits Syst Ⅱ:Express Briefs, 2009, 56(11):810 doi: 10.1109/TCSII.2009.2030357
[26]
Athas W C, Svensson L J, Koller J G, et al. Low-power digital systems based on adiabatic-switching principles. IEEE Trans Very Large Scale Integration (VLSI) Systems, 1994, 2(4):398 doi: 10.1109/92.335009
[27]
Rabaey J M, Chandrakasan A, Nikolic B. Digital integrated circuits: a design perspective. 2nd ed. Prentice Hall Electronics and VLSI Series, Pearson Education, Singapore: Pte Ltd, 2003
[28]
Montanaro J, Witek R T, Anne K, et al. A 160 MHz 32-b 0.5-W CMOS RISC microprocessor. IEEE J Solid-State Circuits, 1996, 31(11):1703 doi: 10.1109/JSSC.1996.542315
[29]
Mahmoodi H, Tirumalashetty V, Cooke M, et al. Ultra low-power clocking scheme using energy recovery and clock gating. IEEE Trans Very Large Scale Integration (VLSI) Systems, 2009, 17(1):33 doi: 10.1109/TVLSI.2008.2008453
[30]
Mahmoodi-Meinnand H, Afzali-Kusha A, Nourani M. Adiabatic carry look-ahead adder with efficient power clock generator. IEE Proceedings Circuits, Devices and Systems, 2001, 148(5):229 doi: 10.1049/ip-cds:20010439

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    Received: 11 February 2014 Revised: 08 April 2014 Online: Published: 01 September 2014

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      Article Navigation >  Journal of Semiconductors  > 2014  >  35(9): 095001
      Jitendra Kanungo, S. Dasgupta. Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator[J]. Journal of Semiconductors, 2014, 35(9): 095001. doi: 10.1088/1674-4926/35/9/095001 J Kanungo, S. Dasgupta. Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator[J]. J. Semicond., 2014, 35(9): 095001. doi: 10.1088/1674-4926/35/9/095001.Export: BibTex EndNote
      Citation:
      Jitendra Kanungo, S. Dasgupta. Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator[J]. Journal of Semiconductors, 2014, 35(9): 095001. doi: 10.1088/1674-4926/35/9/095001

      J Kanungo, S. Dasgupta. Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator[J]. J. Semicond., 2014, 35(9): 095001. doi: 10.1088/1674-4926/35/9/095001.
      Export: BibTex EndNote
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      Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator

      doi: 10.1088/1674-4926/35/9/095001
      • 1.

        Department of Electronics & Communication Engineering, Jaypee University of Engineering & Technology, Guna-473226, India

      • 2.

        Microelectronics & VLSI Group, Department of Electronics & Communication Engineering Indian Institute of Technology, Roorkee-247667, India

      Funds:

      Project supported by the Special Man-Power Development Programme in VLSI & Related Software, Phase-II (SMDP-II), Ministry of Information Technology, Government of India and author Jitendra Kanungo also acknowledge the JUET, Guna (M.P.)

      the Special Man-Power Development Programme in VLSI & Related Software, Phase-II (SMDP-II), Ministry of Information Technology, Government of India and author Jitendra Kanungo also acknowledge the JUET, Guna (M.P.) 

      More Information
      • Corresponding author: Jitendra Kanungo, Email:jitendra.kanungo@juet.ac.in
      • Received Date: 2014-02-11
      • Revised Date: 2014-04-08
      • Published Date: 2014-09-01

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