J. Semicond. > 2014, Volume 35 > Issue 9 > 095002, doi: 10.1088/1674-4926/35/9/095002
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SEMICONDUCTOR INTEGRATED CIRCUITS

A compact PE memory for vision chips

Cong Shi1, 2, Zhe Chen1, Jie Yang1, Nanjian Wu1, and Zhihua Wang2, 3

+ Author Affiliations

 Corresponding author: Wu Nanjian, Email:nanjian@semi.ac.cn

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Abstract: This paper presents a novel compact memory in the processing element (PE) for single-instruction multiple-data (SIMD) vision chips. The PE memory is constructed with 8×8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm2/bit promises a higher integration level of the processor. A prototype chip with a 64×64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction.

Key words: vision chip, PE, memory architecture, SIMD, edge extraction



[1]
Ishikawa M, Ogawa K, Komoro T. A CMOS vision chip with SIMD processing element array for 1 ms image processing. IEEE Int Solid State Circuits Conf (ISSCC), San Francisco, CA, 1999:206
[2]
Komuro T, Kagami S, Ishikawa M. A dynamically reconfigurable SIMD processor for a vision chip. IEEE J Solid-State Circuits, 2004, 39(1):265 doi: 10.1109/JSSC.2003.820876
[3]
Miao W, Lin Q, Zhang W, et al. A programmable SIMD vision chip for real-time vision applications. IEEE J Solid-State Circuits, 2008, 43(6):1470 doi: 10.1109/JSSC.2008.923621
[4]
Yamashita H, Sodini C. A CMOS imager with a programmable bit-serial column-parallel SIMD/MIMD processor. IEEE Trans Electron Devices, 2009, 56:2534 doi: 10.1109/TED.2009.2030718
[5]
Cheng C, Lin C, Li C, et al. iVisual:an intelligent visual sensor SoC with 2790 fps CMOS image sensor and 205 GOPS/W vision processor. IEEE J Solid-State Circuits, 2009, 44(1):127 doi: 10.1109/JSSC.2008.2007158
[6]
Lopich A, Dudek P. A SIMD cellular processor array vision chip with asynchronous processing capabilities. IEEE Trans Circuits Syst I:Regular Papers, 2011, 58(10):13
[7]
Zhang W, Fu Q, Wu N. A programmable vision chip based on multiple levels of parallel processors. IEEE J Solid-State Circuits, 2011, 46(9):2132 doi: 10.1109/JSSC.2011.2158024
[8]
Shi C, Yang J, Han Y, et al. A 1000 fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network. IEEE Int Solid State Circuits Conf (ISSCC), San Francisco, CA, 2014: 128
Fig. 1.  The PE array architecture

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Fig. 2.  The PE block diagram

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Fig. 3.  The 7-T static latch. (a) Circuit schematic. (b) Timing diagram

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Fig. 4.  The 5-T dynamic latch. (a) Circuit schematic. (b) Timing diagram

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Fig. 5.  Five types of PE memory cell. (a) The static-latch cell. (b) The static-latch cell. (c) The static-master static-slave (SMSS) cell. (d) The dynamic-master dynamic-slave (DMDS) cell. (e) The static-master dynamic-slave (SMDS) cell

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Fig. 6.  (a) The chip microphotograph. (b) PE layout

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Fig. 7.  Image edge extraction on the prototype chip. (a), (c) are original images, and (b), (d) are corresponding results

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Table 1.   Summary of PE memory cell types

Table 2.   Comparison with a synthesized design and other vision chips
[1]
Ishikawa M, Ogawa K, Komoro T. A CMOS vision chip with SIMD processing element array for 1 ms image processing. IEEE Int Solid State Circuits Conf (ISSCC), San Francisco, CA, 1999:206
[2]
Komuro T, Kagami S, Ishikawa M. A dynamically reconfigurable SIMD processor for a vision chip. IEEE J Solid-State Circuits, 2004, 39(1):265 doi: 10.1109/JSSC.2003.820876
[3]
Miao W, Lin Q, Zhang W, et al. A programmable SIMD vision chip for real-time vision applications. IEEE J Solid-State Circuits, 2008, 43(6):1470 doi: 10.1109/JSSC.2008.923621
[4]
Yamashita H, Sodini C. A CMOS imager with a programmable bit-serial column-parallel SIMD/MIMD processor. IEEE Trans Electron Devices, 2009, 56:2534 doi: 10.1109/TED.2009.2030718
[5]
Cheng C, Lin C, Li C, et al. iVisual:an intelligent visual sensor SoC with 2790 fps CMOS image sensor and 205 GOPS/W vision processor. IEEE J Solid-State Circuits, 2009, 44(1):127 doi: 10.1109/JSSC.2008.2007158
[6]
Lopich A, Dudek P. A SIMD cellular processor array vision chip with asynchronous processing capabilities. IEEE Trans Circuits Syst I:Regular Papers, 2011, 58(10):13
[7]
Zhang W, Fu Q, Wu N. A programmable vision chip based on multiple levels of parallel processors. IEEE J Solid-State Circuits, 2011, 46(9):2132 doi: 10.1109/JSSC.2011.2158024
[8]
Shi C, Yang J, Han Y, et al. A 1000 fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network. IEEE Int Solid State Circuits Conf (ISSCC), San Francisco, CA, 2014: 128

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    Received: 25 January 2014 Revised: 10 March 2014 Online: Published: 01 September 2014

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      Article Navigation >  Journal of Semiconductors  > 2014  >  35(9): 095002
      Cong Shi, Zhe Chen, Jie Yang, Nanjian Wu, Zhihua Wang. A compact PE memory for vision chips[J]. Journal of Semiconductors, 2014, 35(9): 095002. doi: 10.1088/1674-4926/35/9/095002 C Shi, Z Chen, J Yang, N J Wu, Z H Wang. A compact PE memory for vision chips[J]. J. Semicond., 2014, 35(9): 095002. doi: 10.1088/1674-4926/35/9/095002.Export: BibTex EndNote
      Citation:
      Cong Shi, Zhe Chen, Jie Yang, Nanjian Wu, Zhihua Wang. A compact PE memory for vision chips[J]. Journal of Semiconductors, 2014, 35(9): 095002. doi: 10.1088/1674-4926/35/9/095002

      C Shi, Z Chen, J Yang, N J Wu, Z H Wang. A compact PE memory for vision chips[J]. J. Semicond., 2014, 35(9): 095002. doi: 10.1088/1674-4926/35/9/095002.
      Export: BibTex EndNote
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      A compact PE memory for vision chips

      doi: 10.1088/1674-4926/35/9/095002
      • 1.

        State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China

      • 2.

        Department of Electronic Engineering, Tsinghua University, Beijing 100084, China

      • 3.

        Institute of Microelectronics, Tsinghua University, Beijing 100084, China

      Funds:

      the National Natural Science Foundation of China 60976023

      the National Natural Science Foundation of China 61234003

      the Special Funds for Major State Basic Research Project of China 2011CB932902

      Project supported by the National Natural Science Foundation of China (Nos. 60976023, 61234003) and the Special Funds for Major State Basic Research Project of China (No. 2011CB932902)

      More Information
      • Corresponding author: Wu Nanjian, Email:nanjian@semi.ac.cn
      • Received Date: 2014-01-25
      • Revised Date: 2014-03-10
      • Published Date: 2014-09-01

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