SEMICONDUCTOR INTEGRATED CIRCUITS

An accurate RLGC circuit model for dual tapered TSV structure

Zhen Wei, Xiaochun Li and Junfa Mao

+ Author Affiliations

 Corresponding author: Wei Zhen, Email:gzweizhen@sjtu.edu.cn

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Abstract: A fast RLGC circuit model with analytical expression is proposed for the dual tapered through-silicon via (TSV) structure in three-dimensional integrated circuits under different slope angles at the wide frequency region. By describing the electrical characteristics of the dual tapered TSV structure, the RLGC parameters are extracted based on the numerical integration method. The RLGC model includes metal resistance, metal inductance, substrate resistance, outer inductance with skin effect and eddy effect taken into account. The proposed analytical model is verified to be nearly as accurate as the Q3D extractor but more efficient.

Key words: tapered TSVRLGC circuit modelnumerical integration methodcurrent continuityeddy effect



[1]
Banerjee K, Souri S J, Kapur P, et al. 3-D ICs:a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proc IEEE, 2001, 89:602 doi: 10.1109/5.929647
[2]
Davis W R, Wilson J, Mick S, et al. Demystifying 3D ICs:the pros and cons of going vertical. Design and Test of Computers IEEE, 2005, 22:498 doi: 10.1109/MDT.2005.136
[3]
Beica R, Siblerud P, Sharbono C, et al. Advanced metallization for 3D integration. Electronics Packaging Technology Conference, 2008, (10):212 http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=4763436
[4]
Yu G. Study of DRIE's application in through silicon via (TSV) technology. Su Zhou University, 2009
[5]
Leung L L W, Chen K J. Microwave characterization and modeling of high aspect ratio through-wafer interconnect vias in silicon substrates. IEEE Trans Microw Theory Tech, 2005, 53:2472 doi: 10.1109/TMTT.2005.852782
[6]
Savidis I, Friedman E G. Electrical modeling and characterization of 3-D vias. IEEE International Symposium on Circuits and Systems, 2008:784 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=4541535&punumber%3D4534149
[7]
Savidis I, Friedman E G. Closed-form expressions of 3-D via resistance, inductance, and capacitance. IEEE Trans Electron Devices, 2009, 56:1873 doi: 10.1109/TED.2009.2026200
[8]
Katti G, Stucchi M, De Meyer K, et al. Electrical modeling and characterization of through silicon via for three-dimensional ICs. IEEE Trans Electron Devices, 2010, 57:256 doi: 10.1109/TED.2009.2034508
[9]
Savidis I, Alam S M, Jain A, et al. Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits. Microelectron J, 2010, 41:9 doi: 10.1016/j.mejo.2009.10.006
[10]
Xu C, Li H, Suaya R, et al. Compact AC modeling and performance analysis of through-silicon vias in 3-D ICs. IEEE Trans Electron Devices, 2010, 57:3405 doi: 10.1109/TED.2010.2076382
[11]
Wang F, Zhu Z, Yang Y, et al. Capacitance characterization of tapered through-silicon-via considering MOS effect. Microelectron J, 2013, 45(2):205 doi: 10.1016/j.mejo.2013.10.015
[12]
Liang Y, Li Y. Closed-form expressions for the resistance and the inductance of different profiles of through-silicon vias. Electron Device Lett, 2011, 32(3):393 doi: 10.1109/LED.2010.2099203
[13]
H Li, Banerjee K. High-frequency analysis of carbon nanotube interconnects and implications for on-chip inductor design. IEEE Trans Electron Devices, 2009, 56:2202 doi: 10.1109/TED.2009.2028395
[14]
Jones D S. The theory of electromagnetism. New York:Macmillan, 1964
[15]
Arfken G B, Weber H J, Ruby L. Mathematical methods for physicists. Vol. 6. New York:Academic Press, 1985
[16]
Abramowitz M, Stegun I A. Handbook of mathematical functions with formulas, graphs, and mathematical tables. National Bureau of Standards Applied Mathematics Series 55, Tenth Printing, 1972
[17]
Hayt W H, Buck J A. Engineering electromagnetics. New York, 2006
Fig. 1.  Lateral view of dual tapered TSVs with its equivalent circuit model.

Fig. 2.  Perspective view of single tapered TSV.

Fig. 3.  Resistance $R$ of the dual tapered TSV structure for slope angle $\alpha$ = 5º, 10º, 15º, 20º, respectively. $a$ = 2.5 $\mu$m, $h$ = 15 $\mu$m.

Fig. 4.  Resistance $R$ at 10 GHz and 100 GHz. Resistance in Ref.[12] timed by 2 named $R[12]$ for the dual tapered TSV structure is also shown as a comparison. $\sigma_{\rm Si}$ = 1000 S/m.

Fig. 5.  Inductance $L$ of dual tapered TSV structure for different slope angles. $a$ = 2.5 $\mu$m, $h$ = 15 $\mu$m.

Fig. 6.  Inductance $L$ at 10 GHz and 100 GHz. Inductance for dual tapered TSV structure in Ref.[12] named $L[12]$ is also shown as a comparison. $\sigma_{\rm Si}$ = 1000 S/m.

Fig. 7.  The total capacitance for different slope angles. $a$ = 2.5 $\mu$m, $h$ = 15 $\mu$m.

Fig. 8.  The total capacitance at 10 GHz and 100 GHz. $\sigma_{\rm Si}$ = 1000 S/m.

Fig. 9.  The conductance for different slope angles. $a$ = 2.5 $\mu$m, $h$ = 15 $\mu$m.

Fig. 10.  The conductance at 10 GHz and 100 GHz. $\sigma_{\rm Si}$ = 1000 S/m.

Fig. 11.  The S21 for dual tapered TSV structure.

Table 1.   Maximum error, RMS and computation time ratio of the proposed model for dual tapered TSV structure with different slope angles at 100 GHz.

[1]
Banerjee K, Souri S J, Kapur P, et al. 3-D ICs:a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proc IEEE, 2001, 89:602 doi: 10.1109/5.929647
[2]
Davis W R, Wilson J, Mick S, et al. Demystifying 3D ICs:the pros and cons of going vertical. Design and Test of Computers IEEE, 2005, 22:498 doi: 10.1109/MDT.2005.136
[3]
Beica R, Siblerud P, Sharbono C, et al. Advanced metallization for 3D integration. Electronics Packaging Technology Conference, 2008, (10):212 http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=4763436
[4]
Yu G. Study of DRIE's application in through silicon via (TSV) technology. Su Zhou University, 2009
[5]
Leung L L W, Chen K J. Microwave characterization and modeling of high aspect ratio through-wafer interconnect vias in silicon substrates. IEEE Trans Microw Theory Tech, 2005, 53:2472 doi: 10.1109/TMTT.2005.852782
[6]
Savidis I, Friedman E G. Electrical modeling and characterization of 3-D vias. IEEE International Symposium on Circuits and Systems, 2008:784 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=4541535&punumber%3D4534149
[7]
Savidis I, Friedman E G. Closed-form expressions of 3-D via resistance, inductance, and capacitance. IEEE Trans Electron Devices, 2009, 56:1873 doi: 10.1109/TED.2009.2026200
[8]
Katti G, Stucchi M, De Meyer K, et al. Electrical modeling and characterization of through silicon via for three-dimensional ICs. IEEE Trans Electron Devices, 2010, 57:256 doi: 10.1109/TED.2009.2034508
[9]
Savidis I, Alam S M, Jain A, et al. Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits. Microelectron J, 2010, 41:9 doi: 10.1016/j.mejo.2009.10.006
[10]
Xu C, Li H, Suaya R, et al. Compact AC modeling and performance analysis of through-silicon vias in 3-D ICs. IEEE Trans Electron Devices, 2010, 57:3405 doi: 10.1109/TED.2010.2076382
[11]
Wang F, Zhu Z, Yang Y, et al. Capacitance characterization of tapered through-silicon-via considering MOS effect. Microelectron J, 2013, 45(2):205 doi: 10.1016/j.mejo.2013.10.015
[12]
Liang Y, Li Y. Closed-form expressions for the resistance and the inductance of different profiles of through-silicon vias. Electron Device Lett, 2011, 32(3):393 doi: 10.1109/LED.2010.2099203
[13]
H Li, Banerjee K. High-frequency analysis of carbon nanotube interconnects and implications for on-chip inductor design. IEEE Trans Electron Devices, 2009, 56:2202 doi: 10.1109/TED.2009.2028395
[14]
Jones D S. The theory of electromagnetism. New York:Macmillan, 1964
[15]
Arfken G B, Weber H J, Ruby L. Mathematical methods for physicists. Vol. 6. New York:Academic Press, 1985
[16]
Abramowitz M, Stegun I A. Handbook of mathematical functions with formulas, graphs, and mathematical tables. National Bureau of Standards Applied Mathematics Series 55, Tenth Printing, 1972
[17]
Hayt W H, Buck J A. Engineering electromagnetics. New York, 2006
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    Received: 28 January 2014 Revised: 25 March 2014 Online: Published: 01 September 2014

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      Zhen Wei, Xiaochun Li, Junfa Mao. An accurate RLGC circuit model for dual tapered TSV structure[J]. Journal of Semiconductors, 2014, 35(9): 095008. doi: 10.1088/1674-4926/35/9/095008 Z Wei, X C Li, J F Mao. An accurate RLGC circuit model for dual tapered TSV structure[J]. J. Semicond., 2014, 35(9): 095008. doi: 10.1088/1674-4926/35/9/095008.Export: BibTex EndNote
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      Zhen Wei, Xiaochun Li, Junfa Mao. An accurate RLGC circuit model for dual tapered TSV structure[J]. Journal of Semiconductors, 2014, 35(9): 095008. doi: 10.1088/1674-4926/35/9/095008

      Z Wei, X C Li, J F Mao. An accurate RLGC circuit model for dual tapered TSV structure[J]. J. Semicond., 2014, 35(9): 095008. doi: 10.1088/1674-4926/35/9/095008.
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      An accurate RLGC circuit model for dual tapered TSV structure

      doi: 10.1088/1674-4926/35/9/095008
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      • Corresponding author: Wei Zhen, Email:gzweizhen@sjtu.edu.cn
      • Received Date: 2014-01-28
      • Revised Date: 2014-03-25
      • Published Date: 2014-09-01

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