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An improved analytical model of 4H-SiC MESFET incorporating bulk and interface trapping effects

M. Hema Lata Rao and N. V. L. Narasimha Murty

+ Author Affiliations

 Corresponding author: M. Hema Lata Rao, E-mail: hlm10@iitbbs.ac.in; N. V. L. Narasimha Murty, E-mail: murtyn@iitbbs.ac.in

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Abstract: An improved analytical model for the current-voltage (I-V) characteristics of the 4H-SiC metal semiconductor field effect transistor (MESFET) on a high purity semi-insulating (HPSI) substrate with trapping and thermal effects is presented. The 4H-SiC MESFET structure includes a stack of HPSI substrates and a uniformly doped channel layer. The trapping effects include both the effect of multiple deep-level traps in the substrate and surface traps between the gate to source/drain. The self-heating effects are also incorporated to obtain the accurate and realistic nature of the analytical model. The importance of the proposed model is emphasised through the inclusion of the recent and exact nature of the traps in the 4H-SiC HPSI substrate responsible for substrate compensation. The analytical model is used to exhibit DC I-V characteristics of the device with and without trapping and thermal effects. From the results, the current degradation is observed due to the surface and substrate trapping effects and the negative conductance introduced by the self-heating effect at a high drain voltage. The calculated results are compared with reported experimental and two-dimensional simulations (Silvaco®-TCAD). The proposed model also illustrates the effectiveness of the gate-source distance scaling effect compared to the gate-drain scaling effect in optimizing 4H-SiC MESFET performance. Results demonstrate that the proposed I-V model of 4H-SiC MESFET is suitable for realizing SiC based monolithic circuits (MMICs) on HPSI substrates.

Key words: SiC MESFETHPSI substratedeep-level trapsMMICs



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Fig. 1.  Schematic cross section of a 4H-SiC MESFET. Both substrate and interface trap (inset) induced depletion regions are shown.

Fig. 2.  Calculated charge density curves for shallow dopants and deep-levels for HPSI 4H-SiC substrate. The Fermi level is found to be at 0.845 eV below the conduction band minimum ($E_{\rm C})$.

Fig. 3.  (Color online) Simulated electron concentration contours to show the drain current injection into the substrate of 4H SiC MESFET at 300 K. The simulation was performed for $V_{\rm G}$ $=$ $-6$ V and $V_{\rm D}$ $=$ 20 V considering (a) trap-free substrate with only the shallow dopants and (b) substrate with the major deep-level traps along with the shallow dopants.

Fig. 4.  Simulated vertical electric field profile along the cutline $AA^{1}$ of the MESFET for the substrate without and with deep-level traps.

Fig. 5.  (Color online) Simulated electron concentration contours to show the drain current injection into the substrate of 4H SiC MESFET at 300 K. Considering (a) a substrate with the absence of EH$_{6/7}$ and (b) a substrate with the absence of the Z$_{1/2}$ trap.

Fig. 6.  Modeled $I$-$V$ characteristics of 4H-SiC MESFET without and with trapping effects. (a) $I_{\rm D}$-$V_{\rm D}$ characteristics for $V_{\rm G}$ $=$ 0 V and (b) $I_{\rm D}$-$V_{\rm G}$ characteristics for $V_{\rm D}$ $=$ 40 V.

Fig. 7.  Modeled $R_{\rm S}$-$V_{\rm G}$ characteristics for 4H-SiC MESFET at $V_{\rm D}$ $=$ 40 V considering two different $D_{\rm it}$ profiles for the SiO$_{2}$/4H-SiC interface.

Fig. 8.  Comparison of analytical $I_{\rm D}$-$V_{\rm G}$ characteristics of 4H-SiC MESFET with substrate trapping and surface trapping effects at $V_{\rm D}$ $=$ 40 V (a) with two-dimensional simulations (Silvaco$^{\circledR }$ TCAD) of (solid lines-analytical model, symbols-2D simulations) and (b) with reported experimental results.

Fig. 9.  $I$-$V$ characteristics of 4H-SiC MESFET with substrate trapping, surface trapping and self-heating effects for $V_{\rm G}$ $=$ 0 V at (a) $T=$ 300 K and (b) $T=$ 500 K.

Fig. 10.  (a) $I_{\rm D}$-$V_{\rm G}$ characteristics of 4H-SiC MESFET in saturation region ($V_{\rm D}$ $=$ 40 V) with varying $L_{\rm sg}$ and for $L=$ 0.5 $\mu$m and $L_{\rm gd}$ $=$ 1.75 $\mu$m. (b) Saturated drain current of the 4H-SiC MESFET as a function of gate-source and gate-drain scaling. The device is operated at $V_{\rm G}$ $=$ 0 V and $V_{\rm D}$ $=$ 40 V.

Fig. 11.  Effect of substrate and surface trapping effects on the (a) modeled transconductance ($G_{\rm m} )$ of the SiC MESFET operated at $V_{\rm D}$ $=$ 40~V and (b) the modeled drain conductance ($G_{\rm D})$ of the SiC MESFET operated at $V_{\rm G}$ $=$ $-2$ V.

Table 1.   Deep level traps in the HPSI substrate of 4H-SiC MESFET with their position, concentration and capture cross sections[10, 30].

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    Received: 19 August 2014 Revised: Online: Published: 01 January 2015

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      M. Hema Lata Rao, N. V. L. Narasimha Murty. An improved analytical model of 4H-SiC MESFET incorporating bulk and interface trapping effects[J]. Journal of Semiconductors, 2015, 36(1): 014004. doi: 10.1088/1674-4926/36/1/014004 M. H. L. Rao, N. V. L. N. Murty. An improved analytical model of 4H-SiC MESFET incorporating bulk and interface trapping effects[J]. J. Semicond., 2015, 36(1): 014004. doi:  10.1088/1674-4926/36/1/014004.Export: BibTex EndNote
      Citation:
      M. Hema Lata Rao, N. V. L. Narasimha Murty. An improved analytical model of 4H-SiC MESFET incorporating bulk and interface trapping effects[J]. Journal of Semiconductors, 2015, 36(1): 014004. doi: 10.1088/1674-4926/36/1/014004

      M. H. L. Rao, N. V. L. N. Murty. An improved analytical model of 4H-SiC MESFET incorporating bulk and interface trapping effects[J]. J. Semicond., 2015, 36(1): 014004. doi:  10.1088/1674-4926/36/1/014004.
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      An improved analytical model of 4H-SiC MESFET incorporating bulk and interface trapping effects

      doi: 10.1088/1674-4926/36/1/014004
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      • Corresponding author: E-mail: hlm10@iitbbs.ac.in; E-mail: murtyn@iitbbs.ac.in
      • Received Date: 2014-08-19
      • Published Date: 2015-01-25

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