SEMICONDUCTOR DEVICES

Performance enhancement of c-CESL-strained 95-nm-gate NMOSFET usingtrench-based structure

Di Zhao1, Qian Luo1, , Xiangzhan Wang1, Qi Yu1, Wei Cui2 and Kaizhou Tan2

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 Corresponding author: Qian Luo, E-mail: lourqian@uestc.edu.cn

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Abstract: A stress modulation technology using a trench-based structure for strained NMOSFET is reported in this paper. With this technology, NMOSFET can be improved by a compressive contact etch stop layer (CESL), whereas the traditional CESL-strained NMOSFET requires a tensile one. To confirm this idea, a 95-nm-gate device with a-2.5 GPa strained CESL is simulated to investigate the effects of the trench-based structure on channel stress. It is demonstrated that the average longitudinal channel stress is transformed from-333 into 256 MPa, which leads to a significant improvement of the device's I-V performance. For strained CMOS, this approach provides a potential alternative besides dual stress liner technology.

Key words: CESLtrenchstrained NMOSFETSiN



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Fig. 1.  The schematic cross-section of the c-CESL strained NMOSFET with a trench-based structure.

Fig. 2.  The distribution of $\sigma_{xx}$ in (a) the conventional strained device and (b) the trench-based strained device.

Fig. 3.  The channel stress $\sigma_{xx}$ in the conventional and the trench-based strained devices.

Fig. 4.  The schematic representation of the four CESL zones (top-CESL, lateral-CESL, bottom-CESL, and trench-CESL).

Fig. 5.  The distribution of $\sigma _{xx}$ in the trench-based device channel caused by the strained (a) top-CESL, (b) lateral-CESL, (c) bottom-CESL, and (d) trench-CESL. For mirror symmetry, only the right half of the channel region (from the middle of the gate to the drain-side gate edge) is shown here.

Fig. 6.  The $\sigma_{xx}$ in the channel due to the effects of top-CESL, lateral-CESL, bottom-CESL, and trench-CESL.

Fig. 7.  The comparison of the output characteristic curves of the trench-based strained device, the conventional strained device and the unstrained device.

Fig. 8.  The comparison of the transfer characteristic curves of the trench-based strained device, the conventional strained device and the unstrained device.

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    Received: 30 May 2014 Revised: Online: Published: 01 January 2015

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      Di Zhao, Qian Luo, Xiangzhan Wang, Qi Yu, Wei Cui, Kaizhou Tan. Performance enhancement of c-CESL-strained 95-nm-gate NMOSFET usingtrench-based structure[J]. Journal of Semiconductors, 2015, 36(1): 014010. doi: 10.1088/1674-4926/36/1/014010 D Zhao, Q Luo, X Z Wang, Q Yu, W Cui, K Z Tan. Performance enhancement of c-CESL-strained 95-nm-gate NMOSFET usingtrench-based structure[J]. J. Semicond., 2015, 36(1): 014010. doi: 10.1088/1674-4926/36/1/014010.Export: BibTex EndNote
      Citation:
      Di Zhao, Qian Luo, Xiangzhan Wang, Qi Yu, Wei Cui, Kaizhou Tan. Performance enhancement of c-CESL-strained 95-nm-gate NMOSFET usingtrench-based structure[J]. Journal of Semiconductors, 2015, 36(1): 014010. doi: 10.1088/1674-4926/36/1/014010

      D Zhao, Q Luo, X Z Wang, Q Yu, W Cui, K Z Tan. Performance enhancement of c-CESL-strained 95-nm-gate NMOSFET usingtrench-based structure[J]. J. Semicond., 2015, 36(1): 014010. doi: 10.1088/1674-4926/36/1/014010.
      Export: BibTex EndNote

      Performance enhancement of c-CESL-strained 95-nm-gate NMOSFET usingtrench-based structure

      doi: 10.1088/1674-4926/36/1/014010
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      Project supported by the Innovative Fund of State Key Laboratory of Electronic Thin Films and Integrated Devices (No. CXJJ201103), the Fund of Analog Integrated Circuit Key Laboratory (No. 9140C090301120C09035), and the Scientific Research Project of Land and Resources Department of Sichuan Province (No. KJ-2013-12 2200199).

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      • Corresponding author: E-mail: lourqian@uestc.edu.cn
      • Received Date: 2014-05-30
      • Accepted Date: 2014-07-07
      • Published Date: 2015-01-25

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