Abstract: Design of a highly reliable SPARC-V8 processor for space applications requires consideration single-event effects including single event upsets, single event transients, single event latch-up, as well as cumulative effects such as the total ionizing dose (TID). In this paper, the fault tolerance of the SPARC-V8 processor to radiation effects is discussed in detail. The SPARC-V8 processor, fabricated in the 65 nm CMOS process, achieves a frequency of 300 MHz with a core area of 9.78×9.78 mm², and it is demonstrated that its radiation hardened performance is suitable for operating in a space environment through the key elements' experiments, which show TID resistance to 300 krad(Si), SEL immunity to greater than 92.5 MeV·cm²/mg, and an SEU error rate of 2.51×10^-4 per day.

Key words: processor, radiation hardening, fault-tolerant architecture, radiation effects