SEMICONDUCTOR INTEGRATED CIRCUITS

Multi-bits error detection and fast recovery in RISC cores

Jing Wang1, 3, Xing Yang1, Yuanfu Zhao2, Weigong Zhang1, 4, , Jiao Shen1, 3 and Keni Qiu1, 3

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 Corresponding author: Zhang Weigong, Email: zwg771@cnu.edu.cn

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Abstract: The particles-induced soft errors are a major threat to the reliability of microprocessors. Even worse, multi-bits upsets (MBUs) are ever-increased due to the rapidly shrinking feature size of the IC on a chip. Several architecture-level mechanisms have been proposed to protect microprocessors from soft errors, such as dual and triple modular redundancies (DMR and TMR). However, most of them are inefficient to combat the growing multi-bits errors or cannot well balance the critical paths delay, area and power penalty. This paper proposes a novel architecture, self-recovery dual-pipeline (SRDP), to effectively provide soft error detection and recovery with low cost for general RISC structures. We focus on the following three aspects. First, an advanced DMR pipeline is devised to detect soft error, especially MBU. Second, SEU/MBU errors can be located by enhancing self-checking logic into pipelines stage registers. Third, a recovery scheme is proposed with a recovery cost of 1 or 5 clock cycles. Our evaluation of a prototype implementation exhibits that the SRDP can successfully detect particle-induced soft errors up to 100% and recovery is nearly 95%, the other 5% will inter a specific trap.

Key words: MBUSEUSETautomatic recoverypipeline hardened



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Fig. 1.  (a) SRDP architecture. (b) Pipeline register MBU error. (c) Combinational logic SET error.

Fig. 2.  The comparison replace in ME and WR stage.

Fig. 3.  ID/EX stage registers self-checking structure.

Fig. 4.  (a) Structure of error mask mode. (b) Timing diagram of error mask mode.

Fig. 5.  (a) Structure of fast recovery mode. (b) Timing diagram of fast recovery mode.

Fig. 6.  Processor model diagram.

Fig. 7.  Fault inject platform.

Fig. 8.  Performance of the two architectures under fault injection.

Table 1.   SRDP recovery strategy.

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Table 2.   Execution times of the benchmark applications.

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Table 3.   Description of subcategories.

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Table 4.   Execution times of the Dystone applications.

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Table 5.   Comparison of area and performance overhead.

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    Received: 11 June 2015 Revised: Online: Published: 01 November 2015

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      Jing Wang, Xing Yang, Yuanfu Zhao, Weigong Zhang, Jiao Shen, Keni Qiu. Multi-bits error detection and fast recovery in RISC cores[J]. Journal of Semiconductors, 2015, 36(11): 115009. doi: 10.1088/1674-4926/36/11/115009 J Wang, X Yang, Y F Zhao, W G Zhang, J Shen, K N Qiu. Multi-bits error detection and fast recovery in RISC cores[J]. J. Semicond., 2015, 36(11): 115009. doi: 10.1088/1674-4926/36/11/115009.Export: BibTex EndNote
      Citation:
      Jing Wang, Xing Yang, Yuanfu Zhao, Weigong Zhang, Jiao Shen, Keni Qiu. Multi-bits error detection and fast recovery in RISC cores[J]. Journal of Semiconductors, 2015, 36(11): 115009. doi: 10.1088/1674-4926/36/11/115009

      J Wang, X Yang, Y F Zhao, W G Zhang, J Shen, K N Qiu. Multi-bits error detection and fast recovery in RISC cores[J]. J. Semicond., 2015, 36(11): 115009. doi: 10.1088/1674-4926/36/11/115009.
      Export: BibTex EndNote

      Multi-bits error detection and fast recovery in RISC cores

      doi: 10.1088/1674-4926/36/11/115009
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      • Corresponding author: Zhang Weigong, Email: zwg771@cnu.edu.cn
      • Received Date: 2015-06-11
      • Accepted Date: 2015-07-06
      • Published Date: 2015-01-25

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