SEMICONDUCTOR INTEGRATED CIRCUITS

A trimming technique for capacitive SAR ADC as sensor interface

Ke Liu, Zhankun Du, Li Shao and Xiao Ma

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 Corresponding author: Liu Ke,Email:liuke@ime.ac.cn

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Abstract: This work presented a trimming technique and algorithm applied in a capacitive successive approximation register(SAR) analog to digital converter(ADC) for a sensor interface, which can be integrated with the preceding sensor and the following controlling circuit. Without spending a special calibration phase or adding complicated functions, this circuit keeps a 12-bit resolution by trimming the capacitor array. Its merits of low power and small area make it suitable to be embedded in a power and cost sensitive system such as a battery-supplied sensor network node. The prototype 12-bit ADC is implemented by 0.5μm 2P3M CMOS technology, with the wide supply range of 2-5 V, its power consumption is only 300μA at a sampling speed of 200 kHz.

Key words: SARADCtrimmingsensorCMOS



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Fig1.  The systematic diagram of the proposed CR SAR ADC.

Fig2.  The response of the ramp wave input with the 5th bit capacitance error in the least significant bit (LSB) segment: (a) increasing the 5th capacitor and (b) decreasing the 5th capacitor.

Fig3.  The FFT plot of single frequency input with the 5th bit capacitance error in the LSB segment: (a) increasing the 5th capacitor and (b) decreasing the 5th capacitor.

Fig4.  The response of ramp wave input with the 3rd and 5th bit capacitance error in LSB segment: (a) part of the transfer curve and (b) zoom in for small code range.

Fig5.  The proposed trimming algorithm and flow diagram.

Fig6.  The validation of trimming algorithm: the upper is before trimming and the lower is after trimming.

Fig7.  The scheme of sub-CDAC and its connections to trimming capacitor array.

Fig8.  Scheme of trimming capacitor arrays.

Fig9.  MOM capacitor structure.

Fig10.  The circuit scheme of the comparator.

Fig11.  The schematic of cascaded amplifiers. (a) A1 and A2. (b)~A3.

Fig12.  The timing diagram and output method.

Fig13.  Layout of the prototype ADC.

Fig14.  FFT spectrum. (a) Before trimming. (b) After trimming.

Fig15.  Dynamic performance versus input frequency

Table 1.   Specification summary

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Table 2.   Performance comparison

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    Received: 01 April 2015 Revised: Online: Published: 01 December 2015

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      Ke Liu, Zhankun Du, Li Shao, Xiao Ma. A trimming technique for capacitive SAR ADC as sensor interface[J]. Journal of Semiconductors, 2015, 36(12): 125004. doi: 10.1088/1674-4926/36/12/125004 K Liu, Z K Du, L Shao, X Ma. A trimming technique for capacitive SAR ADC as sensor interface[J]. J. Semicond., 2015, 36(12): 125004. doi: 10.1088/1674-4926/36/12/125004.Export: BibTex EndNote
      Citation:
      Ke Liu, Zhankun Du, Li Shao, Xiao Ma. A trimming technique for capacitive SAR ADC as sensor interface[J]. Journal of Semiconductors, 2015, 36(12): 125004. doi: 10.1088/1674-4926/36/12/125004

      K Liu, Z K Du, L Shao, X Ma. A trimming technique for capacitive SAR ADC as sensor interface[J]. J. Semicond., 2015, 36(12): 125004. doi: 10.1088/1674-4926/36/12/125004.
      Export: BibTex EndNote

      A trimming technique for capacitive SAR ADC as sensor interface

      doi: 10.1088/1674-4926/36/12/125004
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      Project supported by the National Natural Science Foundation of China(No. 61204034).

      More Information
      • Corresponding author: Liu Ke,Email:liuke@ime.ac.cn
      • Received Date: 2015-04-01
      • Accepted Date: 2015-06-25
      • Published Date: 2015-01-25

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