J. Semicond. > 2015, Volume 36 > Issue 4 > 044007, doi: 10.1088/1674-4926/36/4/044007
|

SEMICONDUCTOR DEVICES

Device parameter optimization for sub-20 nm node HK/MG-last bulk FinFETs

Miao Xu, Huaxiang Yin, Huilong Zhu, Xiaolong Ma, Weijia Xu, Yongkui Zhang, Zhiguo Zhao, Jun Luo, Hong Yang, Chunlong Li, Lingkuan Meng, Peizheng Hong, Jinjuan Xiang, Jianfeng Gao, Qiang Xu, Wenjuan Xiong, Dahai Wang, Junfeng Li, Chao Zhao, Dapeng Chen, Simon Yang and Tianchun Ye

+ Author Affiliations

 Corresponding author: Miao Xu, E-mail: xumiao@ime.ac.cn; Huaxiang Yin, E-mail: yinhuaxiang@ime.ac.cn

PDF

Abstract: Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate (HK/MG) process are fabricated and the influence of a series of device parameters on the device scaling is investigated. The high and thin Fin structure with a tapered sidewall shows better performance than the normal Fin structure. The punch through stop layer (PTSL) and source drain extension (SDE) doping profiles are carefully optimized. The device without SDE annealing shows a larger drive current than that with SDE annealing due to better Si crystal regrowth in the amorphous Fin structure after source/drain implantation. The band-edged MG has a better short channel effect immunity, but the lower effective work function (EWF) MG shows a larger driveability. A tradeoff choice for different EWF MGs should be carefully designed for the device's scaling.

Key words: bulk FinFET, effective work function (EWF), extension thermal budget, metal gate



[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
Fig. 1.  (a) Process flow for the all-last HK/MG bulk FinFETs in this work. (b) A cross section view of the 30 nm HK/MG stack structure along the direction of the Fin body. (c) and (d) Cross section views of Type-I (Top $W_{\rm Fin}$ $\sim$10 nm and $H_{\rm Fin}$ $\sim$40 nm) and Type-II Fins (Top $W_{\rm Fin}$ $\sim$5 nm and $H_{\rm Fin}$ $\sim$60 nm), respectively.

DownLoad: Full-Size Img PowerPoint
Fig. 2.  $I_{\rm ON}$-$I_{\rm OFF}$ characteristics (a) and $I_{\rm DS}$-$V_{\rm GS}$ transfer curves (b) for the 30 nm all-last HK/MG PMOS FinFETs with different Fin structures.

DownLoad: Full-Size Img PowerPoint
Fig. 3.  $I_{\rm ON}$-$I_{\rm OFF}$ characteristics between 30 nm HK/MG PMOS FinFETs with and without SDE annealing. An average 25 % ($\sim $20 $\mu $A/um) $I_{\rm ON}$ improved for the device without SDE annealing at $I_{\rm OFF}$ $=$ 3 nA/$\mu $m is observed.

DownLoad: Full-Size Img PowerPoint
Fig. 4.  The relationships between $V_{\rm th}$ and gate lengths for bulk FinFETs with different MGs (MG EWF $=$ 4.95 eV and 5.05 eV).

DownLoad: Full-Size Img PowerPoint
Fig. 5.  $I_{\rm ON}$-$I_{\rm OFF}$ characteristic comparisons of 30 nm HK/MG PMOS FinFETs with different MGs. The average drive current is 19 % ($\sim $25 $\mu $A/um) increasing for Type-B MG FinFETs (EWF $=$ 4.95 eV).

DownLoad: Full-Size Img PowerPoint

Table 1.   Parameters in this work.

DownLoad: CSV
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]

    • Search

    Advanced Search >>

    GET CITATION

    shu

    Export: BibTex EndNote

    Article Metrics

    Article views: 2605 Times PDF downloads: 26 Times Cited by: 0 Times

    History

    Received: 07 January 2014 Revised: Online: Published: 01 April 2015

    Catalog

      Email This Article

      User name:
      Email:*请输入正确邮箱
      Code:*验证码错误
      Send
      Article Navigation >  Journal of Semiconductors  > 2015  >  36(4): 044007
      Miao Xu, Huaxiang Yin, Huilong Zhu, Xiaolong Ma, Weijia Xu, Yongkui Zhang, Zhiguo Zhao, Jun Luo, Hong Yang, Chunlong Li, Lingkuan Meng, Peizheng Hong, Jinjuan Xiang, Jianfeng Gao, Qiang Xu, Wenjuan Xiong, Dahai Wang, Junfeng Li, Chao Zhao, Dapeng Chen, Simon Yang, Tianchun Ye. Device parameter optimization for sub-20 nm node HK/MG-last bulk FinFETs[J]. Journal of Semiconductors, 2015, 36(4): 044007. doi: 10.1088/1674-4926/36/4/044007 M Xu, H X Yin, H L Zhu, X L Ma, W J Xu, Y K Zhang, Z G Zhao, J Luo, H Yang, C L Li, L K Meng, P Z Hong, J J Xiang, J F Gao, Q Xu, W J Xiong, D H Wang, J F Li, C Zhao, D P Chen, S M N Yang, T C Ye. Device parameter optimization for sub-20 nm node HK/MG-last bulk FinFETs[J]. J. Semicond., 2015, 36(4): 044007. doi: 10.1088/1674-4926/36/4/044007.Export: BibTex EndNote
      Citation:
      Miao Xu, Huaxiang Yin, Huilong Zhu, Xiaolong Ma, Weijia Xu, Yongkui Zhang, Zhiguo Zhao, Jun Luo, Hong Yang, Chunlong Li, Lingkuan Meng, Peizheng Hong, Jinjuan Xiang, Jianfeng Gao, Qiang Xu, Wenjuan Xiong, Dahai Wang, Junfeng Li, Chao Zhao, Dapeng Chen, Simon Yang, Tianchun Ye. Device parameter optimization for sub-20 nm node HK/MG-last bulk FinFETs[J]. Journal of Semiconductors, 2015, 36(4): 044007. doi: 10.1088/1674-4926/36/4/044007

      M Xu, H X Yin, H L Zhu, X L Ma, W J Xu, Y K Zhang, Z G Zhao, J Luo, H Yang, C L Li, L K Meng, P Z Hong, J J Xiang, J F Gao, Q Xu, W J Xiong, D H Wang, J F Li, C Zhao, D P Chen, S M N Yang, T C Ye. Device parameter optimization for sub-20 nm node HK/MG-last bulk FinFETs[J]. J. Semicond., 2015, 36(4): 044007. doi: 10.1088/1674-4926/36/4/044007.
      Export: BibTex EndNote
      shu

      Device parameter optimization for sub-20 nm node HK/MG-last bulk FinFETs

      doi: 10.1088/1674-4926/36/4/044007

      • Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

      Funds:

      Project supported by the National 02 IC Projects and the Opening Project of Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences.

      More Information

      Catalog

        Journal of Semiconductors © 2017 All Rights Reserved   京ICP备05085259号-2

        /

        DownLoad:  Full-Size Img  PowerPoint
        Return
        Return