SEMICONDUCTOR INTEGRATED CIRCUITS

The impact of process variations on input impedance and mitigation using a circuit technique in FinFET-based LNA

D. Suresh1, K. K. Nagarajan2 and R. Srinivasan3

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 Corresponding author: D. Suresh, E-mail: dsureshh89@gmail.com

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Abstract: The effect of process variations of a FinFET-based low noise amplifier (LNA) are mitigated by using the device in an independently driven mode, i.e. an independently driven double gate (IDDG) FinFET. A 45 nm gate length IDDG FinFET-based cascoded LNA, operating at 5 GHz, is designed and studied to assess the impact of process variation on the LNA performance metrics such as input impedance, gain and noise figure. Four geometrical parameters, gate length, channel width, gate oxide thickness and fin width, and one non-geometrical parameter, channel doping concentration, are considered in the study. The effect of these variations on the input impedance (the desired value is 50 Ω purely real) of the LNA is compensated by the second gate bias of the IDDG FinFET.

Key words: FinFETLNAprocess variationT-SPICE



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Fig. 1.  The LNA circuit considered in this study.

Fig. 2.  The real part of the input impedance.

Fig. 3.  The imaginary part of the input impedance.

Fig. 4.  Voltage gain.

Fig. 5.  Noise figure.

Fig. 6.  The LNA circuit considered for process variation compensation.

Fig. 7.  The simple IDDG Device used to study the effect of gate 2 bias voltages on input impedance.

Fig. 8.  Variation of input impedance as a function of gate 2 bias voltage (while fixing gate 1 at 0.5 V).

Fig. 9.  Compensation method for mismatched input impedance (0: No change, $-$ reduces, $+$ increases).

Fig. 10.  Impact of $R_{\rm B}$ on input impedance.

Fig. 11.  Impact of $R_{\rm e}$ on input impedance.

Table 1.   The components used in the LNA design.

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Table 2.   Simulation results for the FinFET based LNA.

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Table 3.   The parameters considered for process variation on the FinFET- based LNA.

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Table 4.   16 runs of PBE.

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Table 5.   The impact of process variation on the LNA parameters.

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Table 6.   Various cases of input impedance.

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Table 7.   The effect of process variation on Re[$Z_{\rm in}$] and Im[$Z_{\rm in}$] and its compensation.

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Table 8.   The impact of $R_{\rm B}$ and $R_{\rm e}$ on the input impedance before and after matching.

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    Received: 09 September 2014 Revised: Online: Published: 01 April 2015

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      D. Suresh, K. K. Nagarajan, R. Srinivasan. The impact of process variations on input impedance and mitigation using a circuit technique in FinFET-based LNA[J]. Journal of Semiconductors, 2015, 36(4): 045002. doi: 10.1088/1674-4926/36/4/045002 D. Suresh, K. K. Nagarajan, R. Srinivasan. The impact of process variations on input impedance and mitigation using a circuit technique in FinFET-based LNA[J]. J. Semicond., 2015, 36(4): 045002. doi: 10.1088/1674-4926/36/4/045002.Export: BibTex EndNote
      Citation:
      D. Suresh, K. K. Nagarajan, R. Srinivasan. The impact of process variations on input impedance and mitigation using a circuit technique in FinFET-based LNA[J]. Journal of Semiconductors, 2015, 36(4): 045002. doi: 10.1088/1674-4926/36/4/045002

      D. Suresh, K. K. Nagarajan, R. Srinivasan. The impact of process variations on input impedance and mitigation using a circuit technique in FinFET-based LNA[J]. J. Semicond., 2015, 36(4): 045002. doi: 10.1088/1674-4926/36/4/045002.
      Export: BibTex EndNote

      The impact of process variations on input impedance and mitigation using a circuit technique in FinFET-based LNA

      doi: 10.1088/1674-4926/36/4/045002
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      Project supported by the Defense Research Development Organization (DRDO), Government of India.

      More Information
      • Corresponding author: E-mail: dsureshh89@gmail.com
      • Received Date: 2014-09-09
      • Accepted Date: 2014-11-21
      • Published Date: 2015-01-25

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