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A single channel, 6-bit 410-MS/s 3bits/stage asynchronous SAR ADC based on resistive DAC

Xue Han, Qi Wei, Huazhong Yang and Hui Wang

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 Corresponding author: Xue Han, E-mail: snowhx1988@163.com

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Abstract: This paper presents a single channel, low power 6-bit 410-MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) for ultrawide bandwidth (UWB) communication, prototyped in a SMIC 65-nm process. Based on the 3 bits/stage structure, resistive DAC, and the modified asynchronous successive approximation register control logic, the proposed ADC attains a peak spurious-free dynamic range (SFDR) of 41.95 dB, and a signal-to-noise and distortion ratio (SNDR) of 28.52 dB for 370 MS/s. At the sampling rate of 410 MS/s, this design still performs well with a 40.71-dB SFDR and 30.02-dB SNDR. A four-input dynamic comparator is designed so as to decrease the power consumption. The measurement results indicate that this SAR ADC consumes 2.03 mW, corresponding to a figure of merit of 189.17 fJ/step at 410 MS/s.

Key words: analog to digital converterasynchronous logicsuccessive approximation registerbinary-search algorithmdynamic comparator



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Fig. 1.  A block diagram of a conventional SAR.

Fig. 2.  The proposed 3 bits/stage SAR ADC. (a) The block diagram. (b) The control logic. (c) The S/H stage.

Fig. 3.  The circuit of the clock buffer.

Fig. 4.  The simulation result of the clock jitter.

Fig. 5.  The four-input dynamic comparator.

Fig. 6.  The SAR control logic diagram. (a) Synchronous timing. (b) Asynchronous timing. (c) 3 bits/stage timing.

Fig. 7.  A die photograph of the proposed ADC.

Fig. 8.  Measured output spectra (a) Fin $=$ 191.7 kHz and (b) Fin $=$ 14.1 MHz at 370 MS/s.

Fig. 9.  Measured output spectra (a) Fin $=$ 191.7 kHz and (b) Fin $=$ 19.1 MHz at 410 MS/s.

Fig. 10.  Measured SNDR and SFDR versus input frequency at a 370 MS/s sampling rate.

Table 1.   The relationship among the control signal, output and reference.

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Table 2.   Summary of experimental performance and comparison with several designs.

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Table 3.   A comparison of the 2 bits/stage and the 3 bits/stage 6-bit SAR ADC simulation results.

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    Received: 27 October 2014 Revised: Online: Published: 01 May 2015

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      Xue Han, Qi Wei, Huazhong Yang, Hui Wang. A single channel, 6-bit 410-MS/s 3bits/stage asynchronous SAR ADC based on resistive DAC[J]. Journal of Semiconductors, 2015, 36(5): 055010. doi: 10.1088/1674-4926/36/5/055010 X Han, Q Wei, H Z Yang, H Wang. A single channel, 6-bit 410-MS/s 3bits/stage asynchronous SAR ADC based on resistive DAC[J]. J. Semicond., 2015, 36(5): 055010. doi: 10.1088/1674-4926/36/5/055010.Export: BibTex EndNote
      Citation:
      Xue Han, Qi Wei, Huazhong Yang, Hui Wang. A single channel, 6-bit 410-MS/s 3bits/stage asynchronous SAR ADC based on resistive DAC[J]. Journal of Semiconductors, 2015, 36(5): 055010. doi: 10.1088/1674-4926/36/5/055010

      X Han, Q Wei, H Z Yang, H Wang. A single channel, 6-bit 410-MS/s 3bits/stage asynchronous SAR ADC based on resistive DAC[J]. J. Semicond., 2015, 36(5): 055010. doi: 10.1088/1674-4926/36/5/055010.
      Export: BibTex EndNote

      A single channel, 6-bit 410-MS/s 3bits/stage asynchronous SAR ADC based on resistive DAC

      doi: 10.1088/1674-4926/36/5/055010
      Funds:

      Project supported by the National Science Foundation for Young Scientists of China (No.61306029) and the National High Technology Research and Development Program of China (No.2013AA014103).

      More Information
      • Corresponding author: E-mail: snowhx1988@163.com
      • Received Date: 2014-10-27
      • Accepted Date: 2014-11-22
      • Published Date: 2015-01-25

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