SEMICONDUCTOR INTEGRATED CIRCUITS

A 10-bit 120-MS/s pipelined ADC with improved switch and layout scaling strategy

Jia Zhou1, 2, , Lili Xu1, 2, Fule Li1, 2 and Zhihua Wang1, 2

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 Corresponding author: Jia Zhou, Emailjiazhou0220@qq.com

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Abstract: A 10 bit, 120 MS/s two-channel pipelined analog-to digital converter (ADC) is presented. The ADC is featured with improved switch by using the body effect to improve its conduction performance. A scaling down strategy is proposed to get more efficiency in the OTA's layout design. Implemented in a 0.18-μ m CMOS technology, the ADC's prototype occupied an area of 2.05 × 1.83 mm2. With a sampling rate of 120-MS/s and an input of 4.9 MHz, the ADC achieves a spurious-free-dynamic range of 74.32 dB and signal-to-noise-and-distortion ratio of 55.34 dB, while consuming 220-mW/channel at 3-V supply.

Key words: ADCpipelinebody-effectscaling downparallel



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Fig1.  The architecture of the ADC.

Fig2.  The ideal transfer curve.

Fig3.  (a) The conventional MDAC with unit capacitors. (b) The MDAC with lower reference. (c) The proposed MDAC.

Fig4.  The on-chip voltage reference circuit.

Fig5.  (a) The main stage of the OTA. (b) The CMFB of the OTA.

Fig6.  Stages scaling down.

Fig7.  FFT analysis of single channel.

Fig8.  DNL and INL versus code.

Fig9.  (Color online) Measured SNDR,SNR and SFDR versus input frequency at (a) 120 MS/s and (b) 125 MS/s.

Fig10.  Die photograph.

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Table 1.   Key data for the proposed pipeline ADC and the comparison.

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    Received: 20 January 2015 Revised: Online: Published: 01 August 2015

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      Jia Zhou, Lili Xu, Fule Li, Zhihua Wang. A 10-bit 120-MS/s pipelined ADC with improved switch and layout scaling strategy[J]. Journal of Semiconductors, 2015, 36(8): 085008. doi: 10.1088/1674-4926/36/8/085008 J Zhou, L L Xu, F L Li, Z H Wang. A 10-bit 120-MS/s pipelined ADC with improved switch and layout scaling strategy[J]. J. Semicond., 2015, 36(8): 085008. doi: 10.1088/1674-4926/36/8/085008.Export: BibTex EndNote
      Citation:
      Jia Zhou, Lili Xu, Fule Li, Zhihua Wang. A 10-bit 120-MS/s pipelined ADC with improved switch and layout scaling strategy[J]. Journal of Semiconductors, 2015, 36(8): 085008. doi: 10.1088/1674-4926/36/8/085008

      J Zhou, L L Xu, F L Li, Z H Wang. A 10-bit 120-MS/s pipelined ADC with improved switch and layout scaling strategy[J]. J. Semicond., 2015, 36(8): 085008. doi: 10.1088/1674-4926/36/8/085008.
      Export: BibTex EndNote

      A 10-bit 120-MS/s pipelined ADC with improved switch and layout scaling strategy

      doi: 10.1088/1674-4926/36/8/085008
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      • Corresponding author: Emailjiazhou0220@qq.com
      • Received Date: 2015-01-20
      • Accepted Date: 2015-03-02
      • Published Date: 2015-01-25

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