SEMICONDUCTOR INTEGRATED CIRCUITS

High performance 14-bit pipelined redundant signed digit ADC

Swina Narula and Sujata Pandey

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 Corresponding author: Sujata Pandey, Email: spandey@amity.edu

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Abstract: A novel architecture of a pipelined redundant-signed-digit analog to digital converter(RSD-ADC) is presented featuring a high signal to noise ratio(SNR), spurious free dynamic range(SFDR) and signal to noise plus distortion(SNDR) with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC(residue amplification circuit) stages. With the proposed architecture of ADC, SNDR obtained is 85.89 dB, SNR is 85.9 dB and SFDR obtained is 102.8 dB at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.

Key words: pipelined ADCMDACnon-ideal errorssignal to noise ratio(SNR)spurious free dynamic range(SFDR)signal to noise plus distortion(SNDR)



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Fig. 1.  (a) 14-bit pipelined ADC with a single stage architecture. (b) Implementation of 1-bit pipelined ADC.

Fig. 2.  Residue output of stage 1.

Fig. 3.  (Color online) Ideal output with 0.7 V input at stage 1.

Fig. 4.  Residue voltage with comparator offset.

Fig. 5.  (Color online) Digital output due to comparator error at stage 2.

Fig. 6.  (a) 1.5 bit pipelined ADC where each stage produces 2 bits. (b) 1.5-bit per stage SC implementation.

Fig. 7.  Residue voltage for 1.5 bit pipelined ADC.

Fig. 8.  Digital output of 1.5 bit pipelined ADC (7 stage pipelined).

Fig. 9.  (Color online) 1.5-bit pipelined ADC Architecture which removes comparator error at stage 2.

Fig. 10.  Existing methodology of digital correction logic for 14-bit pipelined ADC.

Fig. 11.  Proposed architecture of digital error correction logic (4-bit).

Fig. 12.  (Color online) Capacitor mismatch error.

Fig. 13.  (Color online) Waveform showing the effect of comparator offset.

Fig. 14.  (Color online) Op-amp low gain error.

Fig. 15.  Op-amp offset error.

Fig. 16.  1024 point FFT showing various results.

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Table 1.   Comparison of the performance of proposed model with other models of pipelined ADC.

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    Received: 12 July 2015 Revised: Online: Published: 01 March 2016

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      Swina Narula, Sujata Pandey. High performance 14-bit pipelined redundant signed digit ADC[J]. Journal of Semiconductors, 2016, 37(3): 035001. doi: 10.1088/1674-4926/37/3/035001 S Narula, Sujata Pandey. High performance 14-bit pipelined redundant signed digit ADC[J]. J. Semicond., 2016, 37(3): 035001. doi: 10.1088/1674-4926/37/3/035001.Export: BibTex EndNote
      Citation:
      Swina Narula, Sujata Pandey. High performance 14-bit pipelined redundant signed digit ADC[J]. Journal of Semiconductors, 2016, 37(3): 035001. doi: 10.1088/1674-4926/37/3/035001

      S Narula, Sujata Pandey. High performance 14-bit pipelined redundant signed digit ADC[J]. J. Semicond., 2016, 37(3): 035001. doi: 10.1088/1674-4926/37/3/035001.
      Export: BibTex EndNote

      High performance 14-bit pipelined redundant signed digit ADC

      doi: 10.1088/1674-4926/37/3/035001
      More Information
      • Corresponding author: Sujata Pandey, Email: spandey@amity.edu
      • Received Date: 2015-07-12
      • Accepted Date: 2015-09-01
      • Published Date: 2016-01-25

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