SEMICONDUCTOR DEVICES

From parabolic approximation to evanescent mode analysis on SOI MOSFET

Xiaolong Li1, , Liuhong Ma2, Yuanfei Ai1, 2 and Weihua Han2

+ Author Affiliations

 Corresponding author: Xiaolong Li, Email:xxdailong@163.com

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Abstract: Subthreshold conduction is governed by the potential distribution. We focus on full two-dimensional (2D) analytical modeling in order to evaluate the 2D potential profile within the active area of FinFET structure. Surfaces and interfaces, which are key nanowire elements, are carefully studied. Different structures have different boundary conditions, and therefore different effects on the potential distributions. A range of models in FinFET are reviewed in this paper. Parabolic approximation and evanescent mode are two different basic math methods to simplify the Poisson's equation. Both superposition method and parabolic approximation are widely used in heavily doped devices. It is helpful to learn performances of MOSFETs with different structures. These two methods achieved improvement to face different structures from heavily doped devices or lightly doped devices to junctionless transistors.

Key words: FinFETPoisson's equationparabolic approximationchannel potentialnatural length



[1]
Chang L, Hu C. MOSFET scaling into the 10 nm regime. Superlattices Microstruct, 2000, 28(6):351
[2]
Young K K. Analysis of conduction in fully depleted SOI MOSFET's. IEEE Trans Electron Devices, 1989, 36(3):504 doi: 10.1109/16.19960
[3]
Yan R H, Ouimazd A, Lee K F, et al. Scaling the Si MOSFET:from bulk to SOI to bulk. IEEE Trans Electron Devices, 1992, 39(7):1704 doi: 10.1109/16.141237
[4]
Suzuki K, Tanaka T, Tosaka Y, et al. Scaling theory for doublegate SOI MOSFET's. IEEE Trans Electron Devices, 1993, 40(12):2326 doi: 10.1109/16.249482
[5]
Cristoloveanu S. Multiple-gate SOI MOSFETs. Solid-State Electron, 2004, 48:897 doi: 10.1016/j.sse.2003.12.020
[6]
Auth C P, Plummer J D. Scaling theory for cylindrical fullydepleted, surrounding-gate MOSFET's. IEEE Electron Device Lett, 1997, 18(2):74 doi: 10.1109/55.553049
[7]
Frank D J, Taur Y, Wong H P, et al. Generalized scale length for two-dimensional effects in MOSFET's. IEEE Electron Device Lett, 1998, 19(10):385 doi: 10.1109/55.720194
[8]
Oh S H, Monroe D, Hergenrother J M, et al. Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs. IEEE Electron Device Lett, 2000, 21(9):445 doi: 10.1109/55.863106
[9]
Chen Q, Agrawal B, Meindl J D. et al. A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs'. IEEE Trans Electron Devices, 2002, 49(6):1086 doi: 10.1109/TED.2002.1003757
[10]
Auth C P, Plummer J D. Scaling theory for cylindrical, fullydepleted, surrounding-gate MOSFET's. IEEE Electron Device Lett, 1997, 18:74 doi: 10.1109/55.553049
[11]
Tosaka Y, Suzuki K, Sugii T, et al. Scaline-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET's. IEEE Electron Device Lett, 1994, 15(18):466
[12]
Chiang T K. A novel scaling-parameter-dependent subthreshold swing model for double-gate (DG) SOI MOSFETs:including effective conducting path effect (ECPE). Semicond Sci Technol, 2004, 19:1386 doi: 10.1088/0268-1242/19/12/010
[13]
Chiang T K. A scaling theory for fully-depleted, surroundinggate MOSFETs:including effective conducting path effect. Microelectron Eng, 2005, 77:175 doi: 10.1016/j.mee.2004.10.005
[14]
Chen Q, Harrel E M, Meindl J D. A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs. IEEE Trans Electron Devices, 2003, 50(7):1631 doi: 10.1109/TED.2003.813906
[15]
Monoroe D, Hergenrother J M. Evanescent-mode analysis of short-channel effects in fully depleted SOI and refated MOSFETs. Proceedings 1998 IEEE International SOI Conference, 1998:157
[16]
Woo J C, Terrill K W, Vasudev P K, et al. Two-dimensional analytic modeling of very thin SOI MOSFET's. IEEE Trans Electron Devices, 1990, 37(9):1999 doi: 10.1109/16.57162
[17]
Hamid H A, Guitart J R, Kilchytska V, et al. A 3-D analytical physically based model for the subthreshold swing in undoped trigate FinFETs. IEEE Trans Electron Devices, 2007, 54(9):2487 doi: 10.1109/TED.2007.902415
[18]
Hamid H A, Iñíguez B, Guitart J R, et al. Analytical model of the threshold voltage and subthreshold swing of undoped cylindrical gate-all-around-based MOSFETs. IEEE Trans Electron Devices, 2007, 54(3):572 doi: 10.1109/TED.2006.890595
[19]
Havaldar D S, Katti G. Subthreshold current model of FinFETs based on analytical solution of 3-D Poisson's equation. IEEE Trans Electron Devices, 2006, 53(4):737 doi: 10.1109/TED.2006.870874
[20]
Tosaka Y, K. Suzuki, Sugii T, et al. Scaline-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET's. IEEE Electron Device Lett, 1994, 15:466 doi: 10.1109/55.334669
[21]
Suzuki K, Tanaka T, Tosaka Y, et al. Scaling theory for doublegate SOI MOSFETs. IEEE Trans Electron Devices, 1993, 40:2326 doi: 10.1109/16.249482
[22]
Jazaeri F, Barbut L, Koukab A, et al. Analytical model for ultrathin body junctionless symmetric double gate MOSFETs in subthreshold regime. Solid-State Electron, 2013, 82:103 doi: 10.1016/j.sse.2013.02.001
[23]
Jin X, Liu X, Kwon H I, et al. A subthreshold current model for nanoscale short channel junctionless MOSFETs applicable to symmetric and asymmetric double-gate structure. Solid-State Electron, 2013, 82:77 doi: 10.1016/j.sse.2013.02.004
[24]
Holtij T, Schwarz A, Kloes A, et al. 2D analytical potential modeling of junctionless DG MOSFETS in subthreshold region including proposal for calculating the threshold voltage. IEEE 13th International Conference on Ultimate Integration on Silicon (ULIS), 2012:81
[25]
Colinge J P. Multiple-gate SOI MOSFETs. Solid-State Electron, 2004, 48:897 doi: 10.1016/j.sse.2003.12.020
[26]
El Hamid H A, Guitart J R, Iñíguez B. Two-dimensional analytical threshold voltage and subthreshold swing models of undoped symmetric double-gate MOSFETs. IEEE Trans Electron Devices, 2007, 54:1402 doi: 10.1109/TED.2007.895856
[27]
El Hamid H A, Iniguez B. Two-dimensional analytical threshold voltage roll-off and subthreshold swing models for undoped cylindrical gate all around MOSFET. Solid-State Electron, 2006, 50:805 doi: 10.1016/j.sse.2006.04.020
[28]
Colinge J P, Lee C W, Afzalian A, et al. Nanowire transistors without junctions. Nat Nanotechnol, 2010, 5(3):225 doi: 10.1038/nnano.2010.15
[29]
Kranti A, Yan R, Lee C W, et al. Junctionless nanowire transistor (JNT):properties anddesign guidelines. Proc ESSDERC, 2010:357
[30]
Sarkhel S, Sarkar S K. A comprehensive two dimensional analytical study of a nanoscale linearly graded binary metal alloy gate cylindrical junctionless MOSFET for improved short channel performance. Comput Electron, 2014, 13:925 doi: 10.1007/s10825-014-0609-5
[31]
Holtij T, Graef M, Iñíguez B, et al. Compact model for shortchannel junctionless accumulation mode double gate MOSFETs. IEEE Trans Electron Devices, 2014, 61(2):288 doi: 10.1109/TED.2013.2281615
[32]
Jin X S, Liu X, Kwon H I, et al. A subthreshold current model for nanoscale short channel junctionless MOSFETs applicable to symmetric and asymmetric double-gate structure. Solid-State Electron, 2013, 82:77 doi: 10.1016/j.sse.2013.02.004
[33]
Duarte J P, Choi D J, Choi Y K, et al. A full-range drain current model for double-gate junctionless transistors. IEEE Trans Electron Devices, 2011, 58(12):4219 doi: 10.1109/TED.2011.2169266
[34]
Sallese J M, Chevillon N, Lallement C, et al. Charge-based modeling of junctionless double-gate field-effect transistors. IEEE Trans Electron Devices, 2011, 58(8):2628 doi: 10.1109/TED.2011.2156413
[35]
Jazaeri F, Barbut L, Koukab A, et al. Analytical model for ultrathin body junctionless symmetric double gate MOSFETs in subthreshold regime. Solid-State Electron, 2013, 82:103 doi: 10.1016/j.sse.2013.02.001
[36]
Trevisoli R D, Doria R T, de Souza M, et al. Threshold voltage in junctionless nanowire transistors. Semicond Sci Technol, 2011, 26(10):105009 doi: 10.1088/0268-1242/26/10/105009
[37]
Holtij T, Graef M, Iñígue B, et al. Compact model for shortchannel junctionless accumulation mode double gate MOSFETs. IEEE Trans Electron Devices, 2014, 61(2):288 doi: 10.1109/TED.2013.2281615
[38]
Sarkhel S, Sarkar D K. A comprehensive two dimensional analytical study of a nanoscale. J Comput Electron, 2014, 13(4):925 doi: 10.1007/s10825-014-0609-5
[39]
Choi S J, Moon D I, Kim S, et al. Sensitivity of threshold voltage to nanowire width variation in junctionless transistors. IEEE Electron Device Lett, 2011, 32(2):125 doi: 10.1109/LED.2010.2093506
[40]
Kranti A, Lee C W, Ferain I, et al. Junctionless nanowire transistor (JNT):properties and design guidelines. Solid-State Electron, 2010, 65:33 http://www.academia.edu/11799434/Junctionless_Nanowire_Transistor_JNT_Properties_and_Design_Guidelines
[41]
Lee C W, Ferain I, Afzalian A, et al. Performance estimation of junctionless multigate transistors. Solid State Electron, 2009, 54(2):97 https://www.researchgate.net/profile/Aryan_Afzalian/publication/238925647_Performance_estimation_of_junctionless_multigate_transistors/links/02e7e51d2e58f6df5a000000.pdf
[42]
Gundapaneni S, Ganguly S, Kottantharayil A, et al. Bulk planar junctionless transistor (BPJLT) an attractive device alternative for scaling. IEEE Electron Device Lett, 2011, 32(3):261 doi: 10.1109/LED.2010.2099204
[43]
Rios R, Cappellani A, Armstrong K K, et al. Comparison of junctionless and conventional trigate transistors with Lg down to 26 nm. IEEE Electron Device Lett, 2011, 32(9):1170 doi: 10.1109/LED.2011.2158978
Fig. 1.  Coordinates in multigate FinFET.

Fig. 2.  Coordinates in single gate SOI MOSFET.

Fig. 3.  (Color online) Coordinates in single gate and double gate SOI MOSFET.

Fig. 4.  (Color online) Coordinates in undoped double gate SOI MOSFET.

Fig. 5.  Coordinates in undoped double gate SOI MOSFET.

Table 1.   Different expression of λ in single-gate, double-gate and cylindrical gate all around devices.

[1]
Chang L, Hu C. MOSFET scaling into the 10 nm regime. Superlattices Microstruct, 2000, 28(6):351
[2]
Young K K. Analysis of conduction in fully depleted SOI MOSFET's. IEEE Trans Electron Devices, 1989, 36(3):504 doi: 10.1109/16.19960
[3]
Yan R H, Ouimazd A, Lee K F, et al. Scaling the Si MOSFET:from bulk to SOI to bulk. IEEE Trans Electron Devices, 1992, 39(7):1704 doi: 10.1109/16.141237
[4]
Suzuki K, Tanaka T, Tosaka Y, et al. Scaling theory for doublegate SOI MOSFET's. IEEE Trans Electron Devices, 1993, 40(12):2326 doi: 10.1109/16.249482
[5]
Cristoloveanu S. Multiple-gate SOI MOSFETs. Solid-State Electron, 2004, 48:897 doi: 10.1016/j.sse.2003.12.020
[6]
Auth C P, Plummer J D. Scaling theory for cylindrical fullydepleted, surrounding-gate MOSFET's. IEEE Electron Device Lett, 1997, 18(2):74 doi: 10.1109/55.553049
[7]
Frank D J, Taur Y, Wong H P, et al. Generalized scale length for two-dimensional effects in MOSFET's. IEEE Electron Device Lett, 1998, 19(10):385 doi: 10.1109/55.720194
[8]
Oh S H, Monroe D, Hergenrother J M, et al. Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs. IEEE Electron Device Lett, 2000, 21(9):445 doi: 10.1109/55.863106
[9]
Chen Q, Agrawal B, Meindl J D. et al. A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs'. IEEE Trans Electron Devices, 2002, 49(6):1086 doi: 10.1109/TED.2002.1003757
[10]
Auth C P, Plummer J D. Scaling theory for cylindrical, fullydepleted, surrounding-gate MOSFET's. IEEE Electron Device Lett, 1997, 18:74 doi: 10.1109/55.553049
[11]
Tosaka Y, Suzuki K, Sugii T, et al. Scaline-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET's. IEEE Electron Device Lett, 1994, 15(18):466
[12]
Chiang T K. A novel scaling-parameter-dependent subthreshold swing model for double-gate (DG) SOI MOSFETs:including effective conducting path effect (ECPE). Semicond Sci Technol, 2004, 19:1386 doi: 10.1088/0268-1242/19/12/010
[13]
Chiang T K. A scaling theory for fully-depleted, surroundinggate MOSFETs:including effective conducting path effect. Microelectron Eng, 2005, 77:175 doi: 10.1016/j.mee.2004.10.005
[14]
Chen Q, Harrel E M, Meindl J D. A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs. IEEE Trans Electron Devices, 2003, 50(7):1631 doi: 10.1109/TED.2003.813906
[15]
Monoroe D, Hergenrother J M. Evanescent-mode analysis of short-channel effects in fully depleted SOI and refated MOSFETs. Proceedings 1998 IEEE International SOI Conference, 1998:157
[16]
Woo J C, Terrill K W, Vasudev P K, et al. Two-dimensional analytic modeling of very thin SOI MOSFET's. IEEE Trans Electron Devices, 1990, 37(9):1999 doi: 10.1109/16.57162
[17]
Hamid H A, Guitart J R, Kilchytska V, et al. A 3-D analytical physically based model for the subthreshold swing in undoped trigate FinFETs. IEEE Trans Electron Devices, 2007, 54(9):2487 doi: 10.1109/TED.2007.902415
[18]
Hamid H A, Iñíguez B, Guitart J R, et al. Analytical model of the threshold voltage and subthreshold swing of undoped cylindrical gate-all-around-based MOSFETs. IEEE Trans Electron Devices, 2007, 54(3):572 doi: 10.1109/TED.2006.890595
[19]
Havaldar D S, Katti G. Subthreshold current model of FinFETs based on analytical solution of 3-D Poisson's equation. IEEE Trans Electron Devices, 2006, 53(4):737 doi: 10.1109/TED.2006.870874
[20]
Tosaka Y, K. Suzuki, Sugii T, et al. Scaline-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET's. IEEE Electron Device Lett, 1994, 15:466 doi: 10.1109/55.334669
[21]
Suzuki K, Tanaka T, Tosaka Y, et al. Scaling theory for doublegate SOI MOSFETs. IEEE Trans Electron Devices, 1993, 40:2326 doi: 10.1109/16.249482
[22]
Jazaeri F, Barbut L, Koukab A, et al. Analytical model for ultrathin body junctionless symmetric double gate MOSFETs in subthreshold regime. Solid-State Electron, 2013, 82:103 doi: 10.1016/j.sse.2013.02.001
[23]
Jin X, Liu X, Kwon H I, et al. A subthreshold current model for nanoscale short channel junctionless MOSFETs applicable to symmetric and asymmetric double-gate structure. Solid-State Electron, 2013, 82:77 doi: 10.1016/j.sse.2013.02.004
[24]
Holtij T, Schwarz A, Kloes A, et al. 2D analytical potential modeling of junctionless DG MOSFETS in subthreshold region including proposal for calculating the threshold voltage. IEEE 13th International Conference on Ultimate Integration on Silicon (ULIS), 2012:81
[25]
Colinge J P. Multiple-gate SOI MOSFETs. Solid-State Electron, 2004, 48:897 doi: 10.1016/j.sse.2003.12.020
[26]
El Hamid H A, Guitart J R, Iñíguez B. Two-dimensional analytical threshold voltage and subthreshold swing models of undoped symmetric double-gate MOSFETs. IEEE Trans Electron Devices, 2007, 54:1402 doi: 10.1109/TED.2007.895856
[27]
El Hamid H A, Iniguez B. Two-dimensional analytical threshold voltage roll-off and subthreshold swing models for undoped cylindrical gate all around MOSFET. Solid-State Electron, 2006, 50:805 doi: 10.1016/j.sse.2006.04.020
[28]
Colinge J P, Lee C W, Afzalian A, et al. Nanowire transistors without junctions. Nat Nanotechnol, 2010, 5(3):225 doi: 10.1038/nnano.2010.15
[29]
Kranti A, Yan R, Lee C W, et al. Junctionless nanowire transistor (JNT):properties anddesign guidelines. Proc ESSDERC, 2010:357
[30]
Sarkhel S, Sarkar S K. A comprehensive two dimensional analytical study of a nanoscale linearly graded binary metal alloy gate cylindrical junctionless MOSFET for improved short channel performance. Comput Electron, 2014, 13:925 doi: 10.1007/s10825-014-0609-5
[31]
Holtij T, Graef M, Iñíguez B, et al. Compact model for shortchannel junctionless accumulation mode double gate MOSFETs. IEEE Trans Electron Devices, 2014, 61(2):288 doi: 10.1109/TED.2013.2281615
[32]
Jin X S, Liu X, Kwon H I, et al. A subthreshold current model for nanoscale short channel junctionless MOSFETs applicable to symmetric and asymmetric double-gate structure. Solid-State Electron, 2013, 82:77 doi: 10.1016/j.sse.2013.02.004
[33]
Duarte J P, Choi D J, Choi Y K, et al. A full-range drain current model for double-gate junctionless transistors. IEEE Trans Electron Devices, 2011, 58(12):4219 doi: 10.1109/TED.2011.2169266
[34]
Sallese J M, Chevillon N, Lallement C, et al. Charge-based modeling of junctionless double-gate field-effect transistors. IEEE Trans Electron Devices, 2011, 58(8):2628 doi: 10.1109/TED.2011.2156413
[35]
Jazaeri F, Barbut L, Koukab A, et al. Analytical model for ultrathin body junctionless symmetric double gate MOSFETs in subthreshold regime. Solid-State Electron, 2013, 82:103 doi: 10.1016/j.sse.2013.02.001
[36]
Trevisoli R D, Doria R T, de Souza M, et al. Threshold voltage in junctionless nanowire transistors. Semicond Sci Technol, 2011, 26(10):105009 doi: 10.1088/0268-1242/26/10/105009
[37]
Holtij T, Graef M, Iñígue B, et al. Compact model for shortchannel junctionless accumulation mode double gate MOSFETs. IEEE Trans Electron Devices, 2014, 61(2):288 doi: 10.1109/TED.2013.2281615
[38]
Sarkhel S, Sarkar D K. A comprehensive two dimensional analytical study of a nanoscale. J Comput Electron, 2014, 13(4):925 doi: 10.1007/s10825-014-0609-5
[39]
Choi S J, Moon D I, Kim S, et al. Sensitivity of threshold voltage to nanowire width variation in junctionless transistors. IEEE Electron Device Lett, 2011, 32(2):125 doi: 10.1109/LED.2010.2093506
[40]
Kranti A, Lee C W, Ferain I, et al. Junctionless nanowire transistor (JNT):properties and design guidelines. Solid-State Electron, 2010, 65:33 http://www.academia.edu/11799434/Junctionless_Nanowire_Transistor_JNT_Properties_and_Design_Guidelines
[41]
Lee C W, Ferain I, Afzalian A, et al. Performance estimation of junctionless multigate transistors. Solid State Electron, 2009, 54(2):97 https://www.researchgate.net/profile/Aryan_Afzalian/publication/238925647_Performance_estimation_of_junctionless_multigate_transistors/links/02e7e51d2e58f6df5a000000.pdf
[42]
Gundapaneni S, Ganguly S, Kottantharayil A, et al. Bulk planar junctionless transistor (BPJLT) an attractive device alternative for scaling. IEEE Electron Device Lett, 2011, 32(3):261 doi: 10.1109/LED.2010.2099204
[43]
Rios R, Cappellani A, Armstrong K K, et al. Comparison of junctionless and conventional trigate transistors with Lg down to 26 nm. IEEE Electron Device Lett, 2011, 32(9):1170 doi: 10.1109/LED.2011.2158978
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    Received: 23 March 2016 Revised: 03 September 2016 Online: Published: 01 February 2017

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      Xiaolong Li, Liuhong Ma, Yuanfei Ai, Weihua Han. From parabolic approximation to evanescent mode analysis on SOI MOSFET[J]. Journal of Semiconductors, 2017, 38(2): 024005. doi: 10.1088/1674-4926/38/2/024005 X L Li, L H Ma, Y F Ai, W H Han. From parabolic approximation to evanescent mode analysis on SOI MOSFET[J]. J. Semicond., 2017, 38(2): 024005. doi: 10.1088/1674-4926/38/2/024005.Export: BibTex EndNote
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      Xiaolong Li, Liuhong Ma, Yuanfei Ai, Weihua Han. From parabolic approximation to evanescent mode analysis on SOI MOSFET[J]. Journal of Semiconductors, 2017, 38(2): 024005. doi: 10.1088/1674-4926/38/2/024005

      X L Li, L H Ma, Y F Ai, W H Han. From parabolic approximation to evanescent mode analysis on SOI MOSFET[J]. J. Semicond., 2017, 38(2): 024005. doi: 10.1088/1674-4926/38/2/024005.
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      From parabolic approximation to evanescent mode analysis on SOI MOSFET

      doi: 10.1088/1674-4926/38/2/024005
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      • Corresponding author: Xiaolong Li, Email:xxdailong@163.com
      • Received Date: 2016-03-23
      • Revised Date: 2016-09-03
      • Published Date: 2017-02-01

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