SEMICONDUCTOR INTEGRATED CIRCUITS

A new sensitivity model with blank space for layout optimization

Junping Wang1, Yao Wu1, , Shigang Liu2 and Runsen Xing1

+ Author Affiliations

 Corresponding author: Yao Wu Email:416508212@qq.com

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Abstract: As the technology scales advancing into the nanometer region, the concept of yield has become an increasingly important design metric. To reduce the yield loss caused by local defects, layout optimization can play a critical role. In this paper, we propose a new open sensitivity-based model with consideration of the blank space around the net, and study the corresponding net optimization. The proposed new model not only has a high practicability in the selection of nets to be optimized but also solves the issue of the increase in short critical area brought during the open optimization, which means to reduce the open critical area with no new short critical area produced, and thereby this model can ensure the decrease of total critical area and finally achieves an integrative optimization. Compared with the models available, the experimental results show that our sensitivity model not only consumes less time with concise algorithm but also can deal with irregular layout, which is out of the scope of other models. At the end of this paper, the effectiveness of the new model is verified by the experiment on the randomly selected five metal layers from the synthesized OpenSparc circuit layout.

Key words: blank spacecritical areamissing material defectlayout optimization



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[3]
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[8]
Pan D Z, Cho M, Yuan K. Manufacturability aware routing in nanometer VLSI. Foundations and Trends in Electronic Design Automation, 2010, 4(1):1 doi: 10.1561/1000000015
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Izuka T, Ikeda M, Asada K. Timing-aware cell layout decompaction for yield optimization by critical area minimization. IEEE Trans Very Large Scale Integr Syst, 2007, 15(6):716 doi: 10.1109/TVLSI.2007.898754
[10]
Cross D, Nequist E, Scheer L A. DFM aware, space based router. International Symposium on Physical Design, 2007:18 https://www.researchgate.net/publication/220915685_A_DFM_aware_space_based_router
[11]
Muller D. Optimizing yield in global routing. Proceedings of the 2006 IEEE/ACM international Conference on Computer-aided design, San Jose, California, 2006:480 http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.138.1798&rep=rep1&type=pdf
[12]
Chiluvuri V K R, Koren I. New routing and compaction strategies for yield enhancement. 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1992:325 http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.352.6112
[13]
Hama T, Etoh H. Curvilinear detailed routing with simultaneous wire-spreading and wire-fattening. IEEE Trans Comput-Aided Des Integr Circuits Syst, 1999, 18(11):1646 doi: 10.1109/43.806809
[14]
Cho M, Xiang H, Puri R, et al. Track routing and optimization for yield. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2008, 27(5):872 doi: 10.1109/TCAD.2008.917589
[15]
Kahng A B, Liu B, Mandoiu I I. Non-tree routing for reliability and yield improvement. IEEE/ACM International Conference on Computer Aided Design (ICCAD-2002), 2002:260 http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.91.6168
[16]
Su J Z, Dai W W. Post-route optimization for improved yield using a rubber-band wiring model. 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997:700 http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.461.8200
[17]
Sinha S, Su Q, Wen L N, et al. A new flexible algorithm for random yield improvement. IEEE Trans Semicond Manuf, 2008, 21(1):14 doi: 10.1109/TSM.2007.913187
[18]
Zachariah S T, Chakravarty S. Algorithm to extract two-node bridges. IEEE Trans VLSI Syst, 2003, 11(4):741 doi: 10.1109/TVLSI.2003.816141
[19]
Chen H Y, Chou S J, Wang S L, Chang Y W. A novel wiredensity-driven full-chip routing system for CMP variation control. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2009, 28(2):193 doi: 10.1109/TCAD.2008.2009156
[20]
Cho M, Pan D Z, Hua X, et al. Wire density driven global routing for CMP variation and timing. 2006 IEEE/ACM International Conference on Computer Aided Design, 2006:487 http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.98.6670&rep=rep1&type=pdf
[21]
Shen Y, Zhou Q, Cai Y C, et al. ECP-and CMP-aware detailed routing algorithm for DFM. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2010, 18(1):153 doi: 10.1109/TVLSI.2008.2008020
[22]
Wang J P, Hao Y, Zhang J M. Yield estimation of metallic layers in integrated circuits. Chin Phys B, 2007, 16(6):1796 doi: 10.1088/1009-1963/16/6/054
[23]
Porat R, Dotan K, Hemar S, et al. SEM-based methodology for root cause analysis of wafer edge and bevel defects. 19th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 2008:11 https://www.researchgate.net/publication/4336777_SEM-based_methodology_for_root_cause_analysis_of_wafer_edge_and_bevel_defects
[24]
Scott J, Glenn F, Alexa P, et al. Utilizing design layout information to improve efficiency of SEM defect review sampling. Advanced Semiconductor Manufacturing Conference, 2008:69 https://www.researchgate.net/publication/4336762_Utilizing_Design_Layout_Information_to_Improve_Efficiency_of_SEM_Defect_Review_Sampling
[25]
de Vries D K, Simon P L C. Calibration of open interconnect yield models. 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2003:26 https://www.researchgate.net/publication/232646663_Calibration_of_Open_Interconnect_Yield_Models
[26]
Barnett T S, Bickford J P, Weger A J. Product yield prediction system and critical area database. IEEE Trans Semicond Manuf, 200821(3):337 doi: 10.1109/TSM.2008.2001207
[27]
Ducotey G, Couvrat A, Audran V, et al. In-line methodology for defectivity analysis from dark field wafer inspection to defect root causes analysis using FIB cut. Advanced Semiconductor Manufacturing Conference and Workshop IEEEI/SEMI, 2008:138 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=4529041&punumber%3D4519622
[28]
Allan G A. Yield prediction by sampling IC layout. IEEE Trans Comput-Aided Des Integrd Circuits Syst, 2000, 19(3):359 doi: 10.1109/43.833204
[29]
Allan G A, Walton A J. Yield preduction by sampling with the EYES tool. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 1996:39 https://www.researchgate.net/publication/3673744_Yield_prediction_by_sampling_with_the_EYES_tool
[30]
Allan G A, Walton A J. Efficient critical area estimation for arbitrary defect shapes. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 1997:20 https://www.researchgate.net/publication/3717586_Efficient_critical_area_estimation_for_arbitrary_defect_shapes
[31]
Wang J P, Hao Y. Critical area computation for real defects and arbitrary conductor shapes. Chin Phys B, 2006, 15(7):1621 doi: 10.1088/1009-1963/15/7/041
[32]
Allan G A, Walton A J. Efficient extra material critical area algorithms. IEEE Trans Comput-Aided Des Integr Circuits Syst, 1999, 18(10):1480 doi: 10.1109/43.790624
[33]
Allan G A, Walton A J. Critical area extraction for soft fault estimation. IEEE Trans Semicond Manuf, 1998, 11(1):146 doi: 10.1109/66.661294
[34]
Goncalves F M, Teixeira I C, Teixeira J P. Integrated approach for circuit and fault extraction of VLSI circuits. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 1996:96 http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=572002
[35]
Zachariah S T, Chakravarty S, Roth C D. A novel algorithm to extract two-node bridges. Design Automation Conference, 2000:750 http://ieeexplore.ieee.org/xpl/abstractKeywords.jsp?reload=true&arnumber=855421&sortType%3Dasc_p_Sequence%26filter%3DAND%28p_IS_Number%3A18566%29%26rowsPerPage%3D75
[36]
Wang J P, Hao Y. WCA model and extract algorithm in 65-90 nm technology node. Acta Phys Sin, 2009, 58(06):4267(in Chinese) https://www.researchgate.net/publication/251981838_Open_NSO_modeling_for_DFM
[37]
Ghaida R S, Doniger K, Zarkesh-Ha P. Random yield prediction based on a stochastic layout sensitivity model. IEEE Trans Semicond Manuf, 2009, 22(3):329 doi: 10.1109/TSM.2009.2024821
[38]
Wang J P, Ning P, Wang L, et al. Open NSO modeling for DFM. ICIECS, 2010:1 https://www.researchgate.net/publication/251981838_Open_NSO_modeling_for_DFM
[39]
[40]
Xiao H J, Hao Y, Guo H X. Equivalent circular defect model of real defect outlines in the IC manufacturing process. IEEE Trans Semicond Manuf, 1998, 11(3):432 doi: 10.1109/66.705378
[41]
Gomez S, Moll F. Yield estimation model for lithography hotspot distortions. Electron Lett, 2013, 49(17):1066 doi: 10.1049/el.2013.0469
Fig. 1.  Ideal layout to reflect the net selection standard.

Fig. 2.  Part of sparc_exu_alu layout.

Fig. 3.  SRAM layout with six-transistor.

Fig. 4.  Modified layout with six-transistor.

Table 1.   Sensitivity of the sparc_exu_alu layout from the OpenSparc circuit.

Table 2.   Optimal order of nets for four open sensitivity models.

Table 3.   Optimal results for the four open sensitivity models.

Table 4.   Optimal results for the new sensitivity model.

[1]
Suiter G, Isaac G. Design for manufacturability:a process, not an afterthought. Circuit Tree, 2009, 22(10):16 https://en.wikipedia.org/wiki/Design_for_manufacturability
[2]
Raghvendra S, Hurat P. DFM:linking design and manufacturing. 18th International Conference on VLSI Design, 2005:705 https://www.researchgate.net/publication/4118278_DFM_Linking_design_and_manufacturing
[3]
Chiang C, Kawa J. Three DFM challenges:random defects, thickness variation, and printability variation. IEEE APCCAS on Circuits and Systems, 2006:1099 http://ieeexplore.ieee.org/document/4145589/
[4]
Gopalani S, Garg R, Khatri S P, et al. DFM-aware structured ASIC design. ISIC-2009-12th International Symposium on Integrated Circuits, 2009:29 https://www.researchgate.net/publication/251918687_DFM-aware_structured_ASIC_design
[5]
Bubel I, Maly W, Waas T, et al. AFFCCA:a tool for critical area analysis with circular defects and lithography deformed layout. Defect and Fault Tolerance in VLSI Systems, 1995:10 https://www.computer.org/csdl/proceedings/dft/1995/7107/00/71070010.pdf
[6]
Chia M P, Allan G A, Walton A J. Photolithography expert system for improved estimation of IC critical area. Conference on Microelectronic Manufacturing Yield, Reliability, and Failure Analysis IV, 1998:74 https://www.researchgate.net/publication/241281540_Photolithography_expert_system_for_improved_estimation_of_IC_critical_area
[7]
Gómez S, Moll F, Mauricio J. Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations. J Micro/Nanolithography, MEMS, MOEMS, 2014, 13(3):1016 http://upcommons.upc.edu/handle/2117/26792
[8]
Pan D Z, Cho M, Yuan K. Manufacturability aware routing in nanometer VLSI. Foundations and Trends in Electronic Design Automation, 2010, 4(1):1 doi: 10.1561/1000000015
[9]
Izuka T, Ikeda M, Asada K. Timing-aware cell layout decompaction for yield optimization by critical area minimization. IEEE Trans Very Large Scale Integr Syst, 2007, 15(6):716 doi: 10.1109/TVLSI.2007.898754
[10]
Cross D, Nequist E, Scheer L A. DFM aware, space based router. International Symposium on Physical Design, 2007:18 https://www.researchgate.net/publication/220915685_A_DFM_aware_space_based_router
[11]
Muller D. Optimizing yield in global routing. Proceedings of the 2006 IEEE/ACM international Conference on Computer-aided design, San Jose, California, 2006:480 http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.138.1798&rep=rep1&type=pdf
[12]
Chiluvuri V K R, Koren I. New routing and compaction strategies for yield enhancement. 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1992:325 http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.352.6112
[13]
Hama T, Etoh H. Curvilinear detailed routing with simultaneous wire-spreading and wire-fattening. IEEE Trans Comput-Aided Des Integr Circuits Syst, 1999, 18(11):1646 doi: 10.1109/43.806809
[14]
Cho M, Xiang H, Puri R, et al. Track routing and optimization for yield. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2008, 27(5):872 doi: 10.1109/TCAD.2008.917589
[15]
Kahng A B, Liu B, Mandoiu I I. Non-tree routing for reliability and yield improvement. IEEE/ACM International Conference on Computer Aided Design (ICCAD-2002), 2002:260 http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.91.6168
[16]
Su J Z, Dai W W. Post-route optimization for improved yield using a rubber-band wiring model. 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997:700 http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.461.8200
[17]
Sinha S, Su Q, Wen L N, et al. A new flexible algorithm for random yield improvement. IEEE Trans Semicond Manuf, 2008, 21(1):14 doi: 10.1109/TSM.2007.913187
[18]
Zachariah S T, Chakravarty S. Algorithm to extract two-node bridges. IEEE Trans VLSI Syst, 2003, 11(4):741 doi: 10.1109/TVLSI.2003.816141
[19]
Chen H Y, Chou S J, Wang S L, Chang Y W. A novel wiredensity-driven full-chip routing system for CMP variation control. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2009, 28(2):193 doi: 10.1109/TCAD.2008.2009156
[20]
Cho M, Pan D Z, Hua X, et al. Wire density driven global routing for CMP variation and timing. 2006 IEEE/ACM International Conference on Computer Aided Design, 2006:487 http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.98.6670&rep=rep1&type=pdf
[21]
Shen Y, Zhou Q, Cai Y C, et al. ECP-and CMP-aware detailed routing algorithm for DFM. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2010, 18(1):153 doi: 10.1109/TVLSI.2008.2008020
[22]
Wang J P, Hao Y, Zhang J M. Yield estimation of metallic layers in integrated circuits. Chin Phys B, 2007, 16(6):1796 doi: 10.1088/1009-1963/16/6/054
[23]
Porat R, Dotan K, Hemar S, et al. SEM-based methodology for root cause analysis of wafer edge and bevel defects. 19th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 2008:11 https://www.researchgate.net/publication/4336777_SEM-based_methodology_for_root_cause_analysis_of_wafer_edge_and_bevel_defects
[24]
Scott J, Glenn F, Alexa P, et al. Utilizing design layout information to improve efficiency of SEM defect review sampling. Advanced Semiconductor Manufacturing Conference, 2008:69 https://www.researchgate.net/publication/4336762_Utilizing_Design_Layout_Information_to_Improve_Efficiency_of_SEM_Defect_Review_Sampling
[25]
de Vries D K, Simon P L C. Calibration of open interconnect yield models. 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2003:26 https://www.researchgate.net/publication/232646663_Calibration_of_Open_Interconnect_Yield_Models
[26]
Barnett T S, Bickford J P, Weger A J. Product yield prediction system and critical area database. IEEE Trans Semicond Manuf, 200821(3):337 doi: 10.1109/TSM.2008.2001207
[27]
Ducotey G, Couvrat A, Audran V, et al. In-line methodology for defectivity analysis from dark field wafer inspection to defect root causes analysis using FIB cut. Advanced Semiconductor Manufacturing Conference and Workshop IEEEI/SEMI, 2008:138 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=4529041&punumber%3D4519622
[28]
Allan G A. Yield prediction by sampling IC layout. IEEE Trans Comput-Aided Des Integrd Circuits Syst, 2000, 19(3):359 doi: 10.1109/43.833204
[29]
Allan G A, Walton A J. Yield preduction by sampling with the EYES tool. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 1996:39 https://www.researchgate.net/publication/3673744_Yield_prediction_by_sampling_with_the_EYES_tool
[30]
Allan G A, Walton A J. Efficient critical area estimation for arbitrary defect shapes. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 1997:20 https://www.researchgate.net/publication/3717586_Efficient_critical_area_estimation_for_arbitrary_defect_shapes
[31]
Wang J P, Hao Y. Critical area computation for real defects and arbitrary conductor shapes. Chin Phys B, 2006, 15(7):1621 doi: 10.1088/1009-1963/15/7/041
[32]
Allan G A, Walton A J. Efficient extra material critical area algorithms. IEEE Trans Comput-Aided Des Integr Circuits Syst, 1999, 18(10):1480 doi: 10.1109/43.790624
[33]
Allan G A, Walton A J. Critical area extraction for soft fault estimation. IEEE Trans Semicond Manuf, 1998, 11(1):146 doi: 10.1109/66.661294
[34]
Goncalves F M, Teixeira I C, Teixeira J P. Integrated approach for circuit and fault extraction of VLSI circuits. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 1996:96 http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=572002
[35]
Zachariah S T, Chakravarty S, Roth C D. A novel algorithm to extract two-node bridges. Design Automation Conference, 2000:750 http://ieeexplore.ieee.org/xpl/abstractKeywords.jsp?reload=true&arnumber=855421&sortType%3Dasc_p_Sequence%26filter%3DAND%28p_IS_Number%3A18566%29%26rowsPerPage%3D75
[36]
Wang J P, Hao Y. WCA model and extract algorithm in 65-90 nm technology node. Acta Phys Sin, 2009, 58(06):4267(in Chinese) https://www.researchgate.net/publication/251981838_Open_NSO_modeling_for_DFM
[37]
Ghaida R S, Doniger K, Zarkesh-Ha P. Random yield prediction based on a stochastic layout sensitivity model. IEEE Trans Semicond Manuf, 2009, 22(3):329 doi: 10.1109/TSM.2009.2024821
[38]
Wang J P, Ning P, Wang L, et al. Open NSO modeling for DFM. ICIECS, 2010:1 https://www.researchgate.net/publication/251981838_Open_NSO_modeling_for_DFM
[39]
[40]
Xiao H J, Hao Y, Guo H X. Equivalent circular defect model of real defect outlines in the IC manufacturing process. IEEE Trans Semicond Manuf, 1998, 11(3):432 doi: 10.1109/66.705378
[41]
Gomez S, Moll F. Yield estimation model for lithography hotspot distortions. Electron Lett, 2013, 49(17):1066 doi: 10.1049/el.2013.0469
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    Received: 02 July 2016 Revised: 02 November 2016 Online: Published: 01 June 2017

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      Junping Wang, Yao Wu, Shigang Liu, Runsen Xing. A new sensitivity model with blank space for layout optimization[J]. Journal of Semiconductors, 2017, 38(6): 065003. doi: 10.1088/1674-4926/38/6/065003 J P Wang, Y Wu, S G Liu, R S Xing. A new sensitivity model with blank space for layout optimization[J]. J. Semicond., 2017, 38(6): 065003. doi: 10.1088/1674-4926/38/6/065003.Export: BibTex EndNote
      Citation:
      Junping Wang, Yao Wu, Shigang Liu, Runsen Xing. A new sensitivity model with blank space for layout optimization[J]. Journal of Semiconductors, 2017, 38(6): 065003. doi: 10.1088/1674-4926/38/6/065003

      J P Wang, Y Wu, S G Liu, R S Xing. A new sensitivity model with blank space for layout optimization[J]. J. Semicond., 2017, 38(6): 065003. doi: 10.1088/1674-4926/38/6/065003.
      Export: BibTex EndNote

      A new sensitivity model with blank space for layout optimization

      doi: 10.1088/1674-4926/38/6/065003
      Funds:

      the 111 Project B08038

      the National Natural Science Foundation of China 61173088

      the Science & Technology Program of Xi'an, China CX1248⑤

      Project supported in part by the National Natural Science Foundation of China (No. 61173088), the Science & Technology Program of Xi'an, China (No. CX1248⑤), and the 111 Project (No. B08038)

      More Information
      • Corresponding author: Yao Wu Email:416508212@qq.com
      • Received Date: 2016-07-02
      • Revised Date: 2016-11-02
      • Published Date: 2017-06-01

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