SEMICONDUCTOR INTEGRATED CIRCUITS

Analysis of single event transient pulse-width in 65 nm commercial radiation-hardened logic cell

Haisong Li, Longsheng Wu, Bo Yang and Yihu Jiang

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 Corresponding author: Haisong Li, Email:holibible@126.com

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Abstract: With the critical charge reduced to generate a single event effect (SEE) and high working frequency for a nanometer integrated circuit, the single event effect (SET) becomes increasingly serious for high performance SOC and DSP chips. To analyze the radiation-hardened method of SET for the nanometer integrated circuit, the n+ guard ring and p+ guard ring have been adopted in the layout for a 65 nm commercial radiation-hardened standard cell library. The weakest driving capacity inverter cell was used to evaluate the single event transient (SET) pulse-width distribution. We employed a dual-lane measurement circuit to get more accurate SET's pulse-width. Six kinds of ions, which provide LETs of 12.5, 22.5, 32.5, 42, 63, and 79.5 MeV·cm2/mg, respectively, have been utilized to irradiate the SET test circuit in the Beijing Tandem Accelerator Nuclear Physics National Laboratory. The testing results reveal that the pulse-width of most SETs is shorter than 400 ps in the range of LETeff from 12.5 MeV·cm2/mg to 79.5 MeV·cm2/mg and the pulse-width presents saturation tendency when the effective linear energy transfer (LETeff) value is larger than 40 MeV·cm2/mg. The test results also show that the hardened commercial standard cell's pulse-width concentrates on 33 to 264 ps, which decreases by 40% compared to the pulse-width of the 65 nm commercial unhardened standard cell.

Key words: single event effectsingle event transientradiation-hardenedguard ring, standard cell librarypulse width



[1]
He Y, Chen S, Chen J, et al. Impact of circuit placement on single event transients in 65 nm bulk CMOS technology. IEEE Trans Nucl Sci, 2012, 59(6):2772 doi: 10.1109/TNS.2012.2218256
[2]
Narasimham B, Bhuva B L, Schrimpf R D, et al. Effects of guard bands and well contacts in mitigating long SETs in advanced CMOS processes. IEEE Trans Nucl Sci, 2007, 55(3):1708
[3]
Gadlage M J, Ahlbin J R, Bhuva B L, et al. Single event transient pulse width measurements in a 65-nm bulk CMOS technology at elevated temperatures. IEEE Xplore Reliability Physics Symposium, 2010:763 http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=5488736
[4]
Makino T, Kobayashi D, Hirose K, et al. LET dependence of single event transient pulse-widths in SOI logic cell. IEEE Trans Nucl Sci, 2009, 56(1):202 doi: 10.1109/TNS.2008.2009054
[5]
Ahlbin J R, Gadlage M J, Ball D R, et al. The effect of layout topology on single-event transient pulse quenching in a 65 nm bulk CMOS process. IEEE Trans Nucl Sci, 2011, 57(6):3380
[6]
Du Y, Chen S, Chen J. A layout-level approach to evaluate and mitigate the sensitive areas of multiple SETs in combinational circuits. IEEE Trans Device Mater Reliab, 2014, 14(14):213 http://ieeexplore.ieee.org/articleDetails.jsp?arnumber=6517226
[7]
Sterpone L, Du B Y. Analysis and mitigation of single event effects on flash-based FPGAS. IEEE Test Symposium, 2014:1 http://porto.polito.it/2556149/
[8]
Evans A, Alexandrescu D, Ferlet-Cavrois V, et al. New techniques for SET sensitivity and propagation measurement in flash-based FPGAs. IEEE Trans Nucl Sci, 2014, 61(6):1 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6955860
[9]
Zhao X, Wang L, Yue S. Single event transients of scan flip-flop and an SET-immune redundant delay filter (RDF). European Conference on Radiation and ITS Effects on Components and Systems, 2013:1 http://ieeexplore.ieee.org/iel7/6923027/6937344/06937385.pdf?arnumber=6937385
[10]
Atkinson N M, Ahlbin J R, Witulski A F, et al. Effect of transistor density and charge sharing on single-event transients in 90-nm bulk CMOS. IEEE Trans Nucl Sci, 2011, 58(6):2578 doi: 10.1109/TNS.2011.2168425
[11]
Chen C H, Knag P, Zhang Z. Characterization of heavy-ion-induced single-event effects in 65 nm bulk CMOS ASIC test chips. IEEE Trans Nucl Sci, 2014, 61(5):2694 doi: 10.1109/TNS.2014.2342872
[12]
Velamala J, Livolsi R, Torres M, et al. Design sensitivity of single event transients in scaled logic circuits. IEEE Design Automation Conference, 2011:694 http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005981990
[13]
Gadlage M J, Ahlbin J R, Narasimham B, et al. Scaling trends in SET pulse widths in sub-100 nm bulk CMOS processes. IEEE Trans Nucl Sci, 2010, 57(6):3336 http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005623329/c/main.pdf
[14]
Artola L, Hubert G, Schrimpf R D. Modeling of radiation-induced single event transients in SOI FinFETS. Reliability Physics Symposium, 2013:SE.1.1 http://www.researchgate.net/profile/Laurent_Artola/publication/259590196_Modeling_of_Radiation-Induced_Single_Event_Transients_in_SOI_FinFETS/links/5458c8500cf2bccc4912a633.pdf
[15]
Calomarde A, Amat E, Moll F, et al. A single event transient hardening circuit design technique based on strengthening. Midwest Symposium on Circuits & Systems, 2013:821 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6674775
[16]
Han B G, Guo Z J, Wu L S. A single-event-hardened phase-locked loop using the radiation-hardened-by-design technique. J Semicond, 2012, 33(10):101 doi: 10.1088/1674-4926/33/10/105007/pdf
[17]
Liu B, Chen S, Liang B, et al. Coupled SET pulse injection in a circuit simulator in ultra-deep submicron technology. Chin J Semicond, 2008, 29(9):1819
[18]
Nicolaidis M. Time redundancy based soft-error tolerance to rescue nanometer technologies. Proceedings VLSI Test Symposium, 1999:86 http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=766651
[19]
Balasubramanian A, Bhuva B L, Black J D, et al. RHBD techniques for mitigating effects of single-event hits using guard-gates. IEEE Trans Nucl Sci, 2005, 52(6):2531 doi: 10.1109/TNS.2005.860719
[20]
Ferlet-Cavrois V, Paillet P, Mcmorrow D, et al. New insights into single event transient propagation in chains of inverters——evidence for propagation-induced pulse broadening. IEEE Trans Nucl Sci, 2007, 54(6):2338 doi: 10.1109/TNS.2007.910202
[21]
Cavrois V F, Pouget V, Mcmorrow D, et al. Investigation of the propagation induced pulse broadening (PIPB) effect on single event transients in SOI and bulk inverter chains. IEEE Trans Nucl Sci, 2008, 55(6):2842 doi: 10.1109/TNS.2008.2007724
[22]
Hamad G B, Hasan S R, Mohamed O A, et al. New insights into the single event transient propagation through static and TSPC logic. IEEE Trans Nucl Sci, 2014, 61(4):1618 doi: 10.1109/TNS.2014.2305434
[23]
Huang P, Chen S, Chen J, et al. Single-event pulse broadening after narrowing effect in nano-CMOS logic circuits. IEEE Trans Device Mater Reliab, 2014, 14(3):849 doi: 10.1109/TDMR.2014.2330841
[24]
Yue S G, Zhang X L, Zhao X Y. Single event transient pulse width measurement of 65-nm bulk CMOS circuits. J Semicond, 2015, 36(11):115006 doi: 10.1088/1674-4926/36/11/115006
Fig. 1.  Schematic representation of time redundancy technique; SET pulse width should be smaller than sampling delay ($\Delta t)$ to ensure the technique is effective.

Fig. 2.  Inverter layout that pMOS transistor is enclosed by n$^+$ guard ring, which contacts with VDD, and the nMOS transistor is enclosed by p$^+$ guard ring, which contacts with GND.

Fig. 3.  Test circuit for SET pulse width measurement. The SET pulse originates from Inverter chain under test and propagates through the pulse expanders and pulse captures. Test result is effective when signal 'monitor' is '1' and is ineffective when 'monitor' is '0'.

Fig. 4.  Block diagram of the test pulse generator. The width of test pulse can be calculated on line to eliminate the PVT's influence.

Fig. 5.  The circuit of Inverter chains under test including 8 inverter chains. Each chain has 200 stages.

Fig. 6.  (a)-(f) Counts of SET pulse captured in the test circuits plotted as a function of measured SET pulse-width $T_{\rm {W}}$. (g) Maximum SET pulse width of (a)-(f) as a function of effective LET. (h) Total counts of (a)-(f) as a function of effective LET.

[1]
He Y, Chen S, Chen J, et al. Impact of circuit placement on single event transients in 65 nm bulk CMOS technology. IEEE Trans Nucl Sci, 2012, 59(6):2772 doi: 10.1109/TNS.2012.2218256
[2]
Narasimham B, Bhuva B L, Schrimpf R D, et al. Effects of guard bands and well contacts in mitigating long SETs in advanced CMOS processes. IEEE Trans Nucl Sci, 2007, 55(3):1708
[3]
Gadlage M J, Ahlbin J R, Bhuva B L, et al. Single event transient pulse width measurements in a 65-nm bulk CMOS technology at elevated temperatures. IEEE Xplore Reliability Physics Symposium, 2010:763 http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=5488736
[4]
Makino T, Kobayashi D, Hirose K, et al. LET dependence of single event transient pulse-widths in SOI logic cell. IEEE Trans Nucl Sci, 2009, 56(1):202 doi: 10.1109/TNS.2008.2009054
[5]
Ahlbin J R, Gadlage M J, Ball D R, et al. The effect of layout topology on single-event transient pulse quenching in a 65 nm bulk CMOS process. IEEE Trans Nucl Sci, 2011, 57(6):3380
[6]
Du Y, Chen S, Chen J. A layout-level approach to evaluate and mitigate the sensitive areas of multiple SETs in combinational circuits. IEEE Trans Device Mater Reliab, 2014, 14(14):213 http://ieeexplore.ieee.org/articleDetails.jsp?arnumber=6517226
[7]
Sterpone L, Du B Y. Analysis and mitigation of single event effects on flash-based FPGAS. IEEE Test Symposium, 2014:1 http://porto.polito.it/2556149/
[8]
Evans A, Alexandrescu D, Ferlet-Cavrois V, et al. New techniques for SET sensitivity and propagation measurement in flash-based FPGAs. IEEE Trans Nucl Sci, 2014, 61(6):1 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6955860
[9]
Zhao X, Wang L, Yue S. Single event transients of scan flip-flop and an SET-immune redundant delay filter (RDF). European Conference on Radiation and ITS Effects on Components and Systems, 2013:1 http://ieeexplore.ieee.org/iel7/6923027/6937344/06937385.pdf?arnumber=6937385
[10]
Atkinson N M, Ahlbin J R, Witulski A F, et al. Effect of transistor density and charge sharing on single-event transients in 90-nm bulk CMOS. IEEE Trans Nucl Sci, 2011, 58(6):2578 doi: 10.1109/TNS.2011.2168425
[11]
Chen C H, Knag P, Zhang Z. Characterization of heavy-ion-induced single-event effects in 65 nm bulk CMOS ASIC test chips. IEEE Trans Nucl Sci, 2014, 61(5):2694 doi: 10.1109/TNS.2014.2342872
[12]
Velamala J, Livolsi R, Torres M, et al. Design sensitivity of single event transients in scaled logic circuits. IEEE Design Automation Conference, 2011:694 http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005981990
[13]
Gadlage M J, Ahlbin J R, Narasimham B, et al. Scaling trends in SET pulse widths in sub-100 nm bulk CMOS processes. IEEE Trans Nucl Sci, 2010, 57(6):3336 http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005623329/c/main.pdf
[14]
Artola L, Hubert G, Schrimpf R D. Modeling of radiation-induced single event transients in SOI FinFETS. Reliability Physics Symposium, 2013:SE.1.1 http://www.researchgate.net/profile/Laurent_Artola/publication/259590196_Modeling_of_Radiation-Induced_Single_Event_Transients_in_SOI_FinFETS/links/5458c8500cf2bccc4912a633.pdf
[15]
Calomarde A, Amat E, Moll F, et al. A single event transient hardening circuit design technique based on strengthening. Midwest Symposium on Circuits & Systems, 2013:821 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6674775
[16]
Han B G, Guo Z J, Wu L S. A single-event-hardened phase-locked loop using the radiation-hardened-by-design technique. J Semicond, 2012, 33(10):101 doi: 10.1088/1674-4926/33/10/105007/pdf
[17]
Liu B, Chen S, Liang B, et al. Coupled SET pulse injection in a circuit simulator in ultra-deep submicron technology. Chin J Semicond, 2008, 29(9):1819
[18]
Nicolaidis M. Time redundancy based soft-error tolerance to rescue nanometer technologies. Proceedings VLSI Test Symposium, 1999:86 http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=766651
[19]
Balasubramanian A, Bhuva B L, Black J D, et al. RHBD techniques for mitigating effects of single-event hits using guard-gates. IEEE Trans Nucl Sci, 2005, 52(6):2531 doi: 10.1109/TNS.2005.860719
[20]
Ferlet-Cavrois V, Paillet P, Mcmorrow D, et al. New insights into single event transient propagation in chains of inverters——evidence for propagation-induced pulse broadening. IEEE Trans Nucl Sci, 2007, 54(6):2338 doi: 10.1109/TNS.2007.910202
[21]
Cavrois V F, Pouget V, Mcmorrow D, et al. Investigation of the propagation induced pulse broadening (PIPB) effect on single event transients in SOI and bulk inverter chains. IEEE Trans Nucl Sci, 2008, 55(6):2842 doi: 10.1109/TNS.2008.2007724
[22]
Hamad G B, Hasan S R, Mohamed O A, et al. New insights into the single event transient propagation through static and TSPC logic. IEEE Trans Nucl Sci, 2014, 61(4):1618 doi: 10.1109/TNS.2014.2305434
[23]
Huang P, Chen S, Chen J, et al. Single-event pulse broadening after narrowing effect in nano-CMOS logic circuits. IEEE Trans Device Mater Reliab, 2014, 14(3):849 doi: 10.1109/TDMR.2014.2330841
[24]
Yue S G, Zhang X L, Zhao X Y. Single event transient pulse width measurement of 65-nm bulk CMOS circuits. J Semicond, 2015, 36(11):115006 doi: 10.1088/1674-4926/36/11/115006
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    Received: 29 October 2016 Revised: 15 January 2017 Online: Published: 01 August 2017

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      Haisong Li, Longsheng Wu, Bo Yang, Yihu Jiang. Analysis of single event transient pulse-width in 65 nm commercial radiation-hardened logic cell[J]. Journal of Semiconductors, 2017, 38(8): 085009. doi: 10.1088/1674-4926/38/8/085009 H S Li, L S Wu, B Yang, Y H Jiang. Analysis of single event transient pulse-width in 65 nm commercial radiation-hardened logic cell[J]. J. Semicond., 2017, 38(8): 085009. doi: 10.1088/1674-4926/38/8/085009.Export: BibTex EndNote
      Citation:
      Haisong Li, Longsheng Wu, Bo Yang, Yihu Jiang. Analysis of single event transient pulse-width in 65 nm commercial radiation-hardened logic cell[J]. Journal of Semiconductors, 2017, 38(8): 085009. doi: 10.1088/1674-4926/38/8/085009

      H S Li, L S Wu, B Yang, Y H Jiang. Analysis of single event transient pulse-width in 65 nm commercial radiation-hardened logic cell[J]. J. Semicond., 2017, 38(8): 085009. doi: 10.1088/1674-4926/38/8/085009.
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      Analysis of single event transient pulse-width in 65 nm commercial radiation-hardened logic cell

      doi: 10.1088/1674-4926/38/8/085009
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      • Corresponding author: Haisong Li, Email:holibible@126.com
      • Received Date: 2016-10-29
      • Revised Date: 2017-01-15
      • Published Date: 2017-08-01

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