SPECIAL ISSUE ON Si-BASED MATERIALS AND DEVICES

Carrier transport mechanisms in semiconductor nanostructures and devices

M. A. Rafiq

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 Corresponding author: M. A. Rafiq, Email: aftab@cantab.net

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Abstract: Semiconductor nanostructures have gained importance due to their potential application in future nanoelectronic devices. For such applications, it is extremely important to understand the electrical properties of semiconductor nanostructures. This review presents an overview of techniques to measure the electrical properties of individual and clusters of semiconductor nanostructures using microcopy based techniques or by fabricating metallic electrical contacts using lithography. Then it is shown that current–voltage (I–V) characteristics can be used to determine the conduction mechanism in these nanostructures. It has been explained that various material parameters can be extracted from I–V characteristics. The frequently observed conduction mechanism in these nanostructures such as thermally activated conduction, space charge limited current (SCLC), hopping conduction, Poole Frenkel conduction, Schottky emission and Fowler Nordheim (FN) tunneling are explained in detail.

Key words: semiconductor nanostructureselectrical conductionelectrical contactslithographymicroscopy



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Fig. 1.  (Color online) (a) Schematic diagram of a single nanowire device. (b) SEM image of a silicon nanowire contacted by microfabricated electrodes.

Fig. 2.  (Color online) C-AFM experimental arrangements for electrical measurements of (a) a lateral nanowire and (b) a vertical nanowire.

Fig. 3.  (Color online) I–V curves for three InAs nanowires plotted on a log–log plot. Top inset shows an SEM image of a probe in contact with nanowire. The lower inset shows I–V curves on linear scale. From Ref. [61].

Fig. 4.  I–V characteristics of a 35 × 35 μm2 diode from 300 to 40 K, on a log–log plot. The temperature step is 20 K. The inset shows the I–V characteristics at 300 K, from −8 to 4 V, on a linear scale. (b) Schematic diagram of SCLC transport. The SiO2 potential barriers in the Si nanocrystal film are omitted for clarity. Carriers (holes) are injected from the p-Si substrate into the film. An exponential distribution of traps nt(E) exists in the film. From Ref. [70].

Fig. 5.  Power law fits to the data of Fig. 4 from 280 to 200 K, with a temperature step of 20 K. The fits meet at cross over voltage Vc = 17 V. The inset shows m as a function of inverse temperature. From Ref. [70].

Fig. 6.  Schematic diagram to illustrate the concept of NNH and VRH.

Fig. 7.  (Color online) lnσ versus (1/T)1/4 plot for (a) p-Si nanowires/TiO2 nanoparticles and (b) n-Si nanowires/TiO2 nanoparticles hybrid device. The data clearly obey the 3D Mott variable range hopping mechanism from 170 to 77 K as indicated by the solid line. (c) Minimum hopping distance Rmin versus temperature plot for both devices. Here SiNWs stands for silicon nanowires and NPs stands for nanoparticles. From Ref. [72].

Fig. 8.  (Color online) Schematic diagram of the Poole Frenkel effect. The φPF, Ec and Et represent the Poole Frenkel barrier height, conduction band energy and trap energy respectively.

Fig. 9.  (Color online) Poole Frenkel plot of AlN thin film. From Ref. [92].

Fig. 10.  (Color online) Schematic diagram of Schottky emission.

Fig. 11.  Temperature dependence of a) ideality factor (n) and b) barrier height φb calculated from fitting of the Schottky emission equation of p+-Si nanowires decorated with and without ZnS nanoparticles. Here NWs stand for nanowires and NPs stand for nanoparticles. From Ref. [106].

Fig. 12.  (Color online) Schematic diagram of tunnelling through metal insulator metal structure.

Fig. 13.  (a) JFEE plots of field emission from ZnO nanorod arrays and (b) corresponding FN plots. From Ref. [116].

Fig. 14.  (Color online) (a) Schematic diagram of n-type TFET. (b) Band diagram of the TFET in OFF state and (c) band diagram of the TFET in ON state.

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    Received: 03 June 2017 Revised: 05 August 2017 Online: Uncorrected proof: 25 January 2018Published: 01 June 2018

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      M. A. Rafiq. Carrier transport mechanisms in semiconductor nanostructures and devices[J]. Journal of Semiconductors, 2018, 39(6): 061002. doi: 10.1088/1674-4926/39/6/061002 M. A. Rafiq. Carrier transport mechanisms in semiconductor nanostructures and devices[J]. J. Semicond., 2018, 39(6): 061002. doi: 10.1088/1674-4926/39/6/061002.Export: BibTex EndNote
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      M. A. Rafiq. Carrier transport mechanisms in semiconductor nanostructures and devices[J]. Journal of Semiconductors, 2018, 39(6): 061002. doi: 10.1088/1674-4926/39/6/061002

      M. A. Rafiq. Carrier transport mechanisms in semiconductor nanostructures and devices[J]. J. Semicond., 2018, 39(6): 061002. doi: 10.1088/1674-4926/39/6/061002.
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      Carrier transport mechanisms in semiconductor nanostructures and devices

      doi: 10.1088/1674-4926/39/6/061002
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      • Corresponding author: Email: aftab@cantab.net
      • Received Date: 2017-06-03
      • Revised Date: 2017-08-05
      • Available Online: 2018-06-01
      • Published Date: 2018-06-01

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