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A comparative study of digital low dropout regulators

Mo Huang1, , Yan Lu1 and Rui P. Martins1, 2

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 Corresponding author: Mo Huang, Email: mohuang@um.edu.mo

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Abstract: Granular power management in a power-efficient system on a chip (SoC) requires multiple integrated voltage regulators with a small area, process scalability, and low supply voltage. Conventional on-chip analog low-dropout regulators (ALDOs) can hardly meet these requirements, while digital LDOs (DLDOs) are good alternatives. However, the conventional DLDO, with synchronous control, has inherently slow transient response limited by the power-speed trade-off. Meanwhile, it has a poor power supply rejection (PSR), because the fully turned-on power switches in DLDO are vulnerable to power supply ripples. In this comparative study on DLDOs, first, we compare the pros and cons between ALDO and DLDO in general. Then, we summarize the recent DLDO advanced techniques for fast transient response and PSR enhancement. Finally, we discuss the design trends and possible directions of DLDO.

Key words: low dropout regulator (LDO)digital controlfast transient responsepower supply rejection (PSR)integrated voltage regulator



[1]
Meinerzhagen P A, Tokunaga C, Malavasi A, et al. An energy-efficient graphics processor in 14-nm tri-gate CMOS featuring integrated voltage regulators for fine-grain DVFS, retentive sleep, and VMIN optimization. IEEE J Solid-State Circuits, 2019, 54, 144 doi: 10.1109/JSSC.2018.2875097
[2]
Nasir S B, Gangopadhyay S, Raychowdhury A. A 0.13 μm fully digital low-dropout regulator with adaptive control and reduced dynamic stability for ultra-wide dynamic range. 2015 IEEE International Solid-State Circuits Conference (ISSCC), 2015, 1
[3]
Chong S, Chan P K. A 0.9-μA quiescent current output-capacitorless LDO regulator with adaptive power transistors in 65-nm CMOS. IEEE Trans Circuits Syst I, 2013, 60, 1072 doi: 10.1109/TCSI.2012.2215392
[4]
Lu Y, Wang Y P, Pan Q, et al. A fully-integrated low-dropout regulator with full-spectrum power supply rejection. IEEE Trans Circuits Syst I, 2015, 62, 707 doi: 10.1109/TCSI.2014.2380644
[5]
Huang M, Feng H G, Lu Y. A fully integrated FVF-based low-dropout regulator with wide load capacitance and current ranges. IEEE Trans Power Electron, 2019, 34, 11880 doi: 10.1109/TPEL.2019.2904622
[6]
Cai G G, Zhan C C, Lu Y. A fast-transient-response fully-integrated digital LDO with adaptive current step size control. 2019 IEEE Int Symp Circuits Syst ISCAS, 2019, 1
[7]
Park C J, Onabajo M, Silva-Martinez J. External capacitor-less low drop-out regulator with 25 dB superior power supply rejection in the 0.4–4 MHz range. IEEE J Solid-State Circuits, 2014, 49, 486 doi: 10.1109/JSSC.2013.2289897
[8]
Lu Y, Martins R P, Seng-Pan U, et al. A 312 ps response-time LDO with enhanced super source follower in 28 nm CMOS. Electron Lett, 2016, 52, 1368 doi: 10.1049/el.2016.1719
[9]
Gupta V, Rincon-Mora G A, Raha P. Analysis and design of monolithic, high PSR, linear regulators for SoC applications. IEEE International SOC Conference, 2004, 311
[10]
Okuma Y, Ishida K, Ryu Y, et al. 0.5-V input digital LDO with 98.7% current efficiency and 2.7-μA quiescent current in 65 nm CMOS. IEEE Custom Integrated Circuits Conference, 2010, 1
[11]
Huang M, Lu Y, Sin S W, et al. Limit cycle oscillation reduction for digital low dropout regulators. IEEE Trans Circuits Syst II, 2016, 63, 903 doi: 10.1109/TCSII.2016.2534778
[12]
Nasir S B, Raychowdhury A. On limit cycle oscillations in discrete-time digital linear regulators. 2015 IEEE Applied Power Electronics Conference and Exposition (APEC), 2015, 371
[13]
Huang M, Lu Y, Sin S W, et al. A fully integrated digital LDO with coarse-fine-tuning and burst-mode operation. IEEE Trans Circuits Syst II, 2016, 63, 683 doi: 10.1109/TCSII.2016.2530094
[14]
Salem L G, Warchall J, Mercier P P. A successive approximation recursive digital low-dropout voltage regulator with PD compensation and sub-LSB duty control. IEEE J Solid-State Circuits, 2018, 53, 35 doi: 10.1109/JSSC.2017.2766215
[15]
Huang M, Lu Y, Seng-Pan U, et al. An output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop control. 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, 342
[16]
Huang M, Lu Y, U S P, et al. An analog-assisted tri-loop digital low-dropout regulator. IEEE J Solid-State Circuits, 2018, 53, 20 doi: 10.1109/JSSC.2017.2751512
[17]
Huang M, Lu Y, Lu X. Partial analogue-assisted digital low dropout regulator with transient body-drive and 2.5 × FOM improvement. Electron Lett, 2018, 54, 282 doi: 10.1049/el.2017.4211
[18]
Ma X F, Lu Y, Martins R P, et al. A 0.4 V 430 nA quiescent current NMOS digital LDO with NAND-based analog-assisted loop in 28 nm CMOS. 2018 IEEE International Solid-State Circuits Conference (ISSCC), 2018, 306
[19]
Akram M A, Hong W, Hwang I C. Fast transient fully standard-cell-based all digital low-dropout regulator with 99.97% current efficiency. IEEE Trans Power Electron, 2018, 33, 8011 doi: 10.1109/TPEL.2017.2771942
[20]
Sun X, Boora A, Zhang W B, et al. A 0.6-to-1.1 V computationally regulated digital LDO with 2.79-cycle mean settling time and autonomous runtime gain tracking in 65 nm CMOS. 2019 IEEE International Solid- State Circuits Conference (ISSCC), 2019, 230
[21]
Lee Y J, Jung M Y, Singh S, et al. A 200 mA digital low-drop-out regulator with coarse-fine dual loop in mobile application processors. 2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, 150
[22]
Kim D, Seok M. Fully integrated low-drop-out regulator based on event-driven PI control. 2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, 148
[23]
Otsuga K, Onouchi M, Igarashi Y, et al. An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor. 2012 IEEE International SOC Conference, 2012, 11
[24]
Gangopadhyay S, Somasekhar D, Tschanz J W, et al. A 32 nm embedded, fully-digital, phase-locked low dropout regulator for fine grained power management in digital circuits. IEEE J Solid-State Circuits, 2014, 49, 2684 doi: 10.1109/JSSC.2014.2353798
[25]
Kundu S, Liu M Q, Wen S J, et al. A fully integrated digital LDO with built-in adaptive sampling and active voltage positioning using a beat-frequency quantizer. IEEE J Solid-State Circuits, 2019, 54, 109 doi: 10.1109/JSSC.2018.2870558
[26]
Lee Y H, Peng S Y, Chiu C C, et al. A low quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40 nm SoC for MIPS performance improvement. IEEE J Solid-State Circuits, 2013, 48, 1018 doi: 10.1109/JSSC.2013.2237991
[27]
Yang F, Mok P K T. A nanosecond-transient fine-grained digital LDO with multi-step switching scheme and asynchronous adaptive pipeline control. IEEE J Solid-State Circuits, 2017, 52, 2463 doi: 10.1109/JSSC.2017.2709311
[28]
Lu Y, Huang M, Martins R P. PID control considerations for analog-digital hybrid low-dropout regulators. 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2019, 1
[29]
Kim S T, Shih Y C, Mazumdar K, et al. Enabling wide autonomous DVFS in a 22 nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation. 2015 IEEE International Solid-State Circuits Conference (ISSCC), 2015, 1
[30]
Zhang Y N, Song H X, Zhou R R, et al. A capacitor-less ripple-less hybrid LDO with exponential ratio array and 4000x load current range. IEEE Trans Circuits Syst II, 2019, 66, 36 doi: 10.1109/TCSII.2018.2834899
[31]
Wang X Y, Mercier P P. A dynamically high-impedance charge-pump-based LDO with digital-LDO-like properties achieving a sub-4-fs FoM. IEEE J Solid-State Circuits, 2020, 55, 719 doi: 10.1109/JSSC.2019.2960004
[32]
Nasir S B, Sen S, Raychowdhury A. Switched-mode-control based hybrid LDO for fine-grain power management of digital load circuits. IEEE J Solid-State Circuits, 2018, 53, 569 doi: 10.1109/JSSC.2017.2767183
[33]
Liu X S, Krishnamurthy H K, Na T, et al. A modular hybrid LDO with fast load-transient response and programmable PSRR in 14 nm CMOS featuring dynamic clamp tuning and time-constant compensation. 2019 IEEE International Solid- State Circuits Conference (ISSCC), 2019, 234
[34]
Huang M, Lu Y. An analog-proportional digital-integral multi-loop digital LDO with fast response, improved PSR and zero minimum load current. 2019 IEEE Custom Integrated Circuits Conference (CICC), 2019, 1
[35]
Huang M, Lu Y, Martins R P. An analog-proportional digital-integral multiloop digital LDO with PSR improvement and LCO reduction. IEEE J Solid-State Circuits, 2020, 55, 1637 doi: 10.1109/JSSC.2020.2967540
[36]
Bang S, Lim W, Augustine C, et al. A fully synthesizable distributed and scalable all-digital LDO in 10 nm CMOS. 2020 IEEE International Solid- State Circuits Conference (ISSCC), 2020, 380
[37]
Li Y F, Zhang X Y, Zhang Z, et al. A 0.45-to-1.2-V fully digital low-dropout voltage regulator with fast-transient controller for near/subthreshold circuits. IEEE Trans Power Electron, 2016, 31, 6341 doi: 10.1109/TPEL.2015.2506605
[38]
Oh J, Park J E, Hwang Y H, et al. A 480 mA output-capacitor-free synthesizable digital LDO using CMP-triggered oscillator and droop detector with 99.99% current efficiency, 1.3 ns response time, and 9.8 A/mm2 current density. 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020, 382
[39]
Singh A, Kar M, Chekuri V C K, et al. A digital low-dropout regulator with autotuned PID compensator and dynamic gain control for improved transient performance under process variations and aging. IEEE Trans Power Electron, 2020, 35, 3242 doi: 10.1109/TPEL.2019.2930490
[40]
Ahmed K Z, Krishnamurthy H K, Augustine C, et al. A variation-adaptive integrated computational digital LDO in 22-nm CMOS with fast transient response. IEEE J Solid-State Circuits, 2020, 55, 977 doi: 10.1109/JSSC.2019.2961854
[41]
Lu Y, Yang F, Chen F, et al. A 500 mA analog-assisted digital-LDO-based on-chip distributed power delivery grid with cooperative regulation and IR-drop reduction in 65 nm CMOS. 2018 IEEE International Solid-State Circuits Conference (ISSCC), 2018, 310
[42]
Hershberg B, Weaver S, Sobue K, et al. Ring amplifiers for switched capacitor circuits. IEEE J Solid-State Circuits, 2012, 47, 2928 doi: 10.1109/JSSC.2012.2217865
[43]
Yang F, Mok P K T. A 65 nm inverter-based low-dropout regulator with rail-to-rail regulation and over −20 dB PSR at 0.2 V lowest supply voltage. 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, 106
[44]
Park J E, Hwang J, Oh J, et al. A 0.4-to-1.2 V 0.0057 mm2 55fs-transient-FoM ring-amplifier-based low-dropout regulator with replica-based PSR enhancement. 2020 IEEE International Solid- State Circuits Conference (ISSCC), 2020, 492
[45]
Hazucha P, Karnik T, Bloechel B A, et al. Area-efficient linear regulator with ultra-fast load regulation. IEEE J Solid-State Circuits, 2005, 40, 933 doi: 10.1109/JSSC.2004.842831
[46]
Duong Q H, Nguyen H H, Kong J W, et al. Multiple-loop design technique for high-performance low-dropout regulator. IEEE J Solid-State Circuits, 2017, 52, 2533 doi: 10.1109/JSSC.2017.2717922
Fig. 1.  (Color online) Granular power management in an SoC.

Fig. 2.  (Color online) DLDO requirements in an SoC.

Fig. 3.  Block diagram of (a) ALDO and (b) DLDO.

Fig. 4.  (Color online) The output voltage undershoot analysis of DLDO.

Fig. 5.  (a) Measured LCO of DLDO, (b) small-signal model of DLDO, and (c) root locus of 2-level quantized DLDO.

Fig. 6.  (Color online) Power supply rejection process of a conventional DLDO.

Fig. 7.  Latch-based comparator.

Fig. 8.  Continuous multi-bit quantizer based on (a) current-mirror and (b) inverter.

Fig. 9.  DLDO based on a VCO quantizer.

Fig. 10.  (Color online) Output voltage transient response under I-only, P-only, PI, and PID control.

Fig. 11.  Change CLK when VOUT exceeds the VREF window.

Fig. 12.  (Color online) Analog-assisted loop in (a)[1517], (b)[18], and (c)[31].

Fig. 13.  (a) Analog circuits help PSR improvement and (b) block diagram of the hybrid LDO.

Fig. 14.  Improving PSR using (a) feedforward PSR cancellation[33] and (b) replica loop[34, 35].

Fig. 15.  (Color online) Simulated PSRs of the conventional DLDO, hybrid LDOs without replica loop, and with replica loop.

Fig. 16.  (Color online) Multi-LDOs assisting a neighboring load step.

Table 1.   Features of the quantizers in DLDO design.

TypeContinuous SensingSpeedPower ConsumptionRobustness
Single-bitNoFastLowHigh
Multi-bitCurrent-to-code ADC[21]YesFastHighHigh
Flash ADC[22]YesFastHighHigh
TDC[23]YesFastMediumNeed calibration
VCO+PD[24, 25]YesSlow (1/s effect)MediumHigh
DownLoad: CSV

Table 2.   FoM of speed versus process nodes.

YearProcess (nm)ArchitectureFoM (ps)
2020[39]130ADC + PID63.9
2016[22]65ADC + Event driven20
2016[21]28ADC + Coarse/fine9.57
2020[40]20ADC + Computational6.7
2020[36]10TDC + PID5.2
2017[15]65Analog-assisted0.23
2018[18]28Analog-assisted0.026
DownLoad: CSV
[1]
Meinerzhagen P A, Tokunaga C, Malavasi A, et al. An energy-efficient graphics processor in 14-nm tri-gate CMOS featuring integrated voltage regulators for fine-grain DVFS, retentive sleep, and VMIN optimization. IEEE J Solid-State Circuits, 2019, 54, 144 doi: 10.1109/JSSC.2018.2875097
[2]
Nasir S B, Gangopadhyay S, Raychowdhury A. A 0.13 μm fully digital low-dropout regulator with adaptive control and reduced dynamic stability for ultra-wide dynamic range. 2015 IEEE International Solid-State Circuits Conference (ISSCC), 2015, 1
[3]
Chong S, Chan P K. A 0.9-μA quiescent current output-capacitorless LDO regulator with adaptive power transistors in 65-nm CMOS. IEEE Trans Circuits Syst I, 2013, 60, 1072 doi: 10.1109/TCSI.2012.2215392
[4]
Lu Y, Wang Y P, Pan Q, et al. A fully-integrated low-dropout regulator with full-spectrum power supply rejection. IEEE Trans Circuits Syst I, 2015, 62, 707 doi: 10.1109/TCSI.2014.2380644
[5]
Huang M, Feng H G, Lu Y. A fully integrated FVF-based low-dropout regulator with wide load capacitance and current ranges. IEEE Trans Power Electron, 2019, 34, 11880 doi: 10.1109/TPEL.2019.2904622
[6]
Cai G G, Zhan C C, Lu Y. A fast-transient-response fully-integrated digital LDO with adaptive current step size control. 2019 IEEE Int Symp Circuits Syst ISCAS, 2019, 1
[7]
Park C J, Onabajo M, Silva-Martinez J. External capacitor-less low drop-out regulator with 25 dB superior power supply rejection in the 0.4–4 MHz range. IEEE J Solid-State Circuits, 2014, 49, 486 doi: 10.1109/JSSC.2013.2289897
[8]
Lu Y, Martins R P, Seng-Pan U, et al. A 312 ps response-time LDO with enhanced super source follower in 28 nm CMOS. Electron Lett, 2016, 52, 1368 doi: 10.1049/el.2016.1719
[9]
Gupta V, Rincon-Mora G A, Raha P. Analysis and design of monolithic, high PSR, linear regulators for SoC applications. IEEE International SOC Conference, 2004, 311
[10]
Okuma Y, Ishida K, Ryu Y, et al. 0.5-V input digital LDO with 98.7% current efficiency and 2.7-μA quiescent current in 65 nm CMOS. IEEE Custom Integrated Circuits Conference, 2010, 1
[11]
Huang M, Lu Y, Sin S W, et al. Limit cycle oscillation reduction for digital low dropout regulators. IEEE Trans Circuits Syst II, 2016, 63, 903 doi: 10.1109/TCSII.2016.2534778
[12]
Nasir S B, Raychowdhury A. On limit cycle oscillations in discrete-time digital linear regulators. 2015 IEEE Applied Power Electronics Conference and Exposition (APEC), 2015, 371
[13]
Huang M, Lu Y, Sin S W, et al. A fully integrated digital LDO with coarse-fine-tuning and burst-mode operation. IEEE Trans Circuits Syst II, 2016, 63, 683 doi: 10.1109/TCSII.2016.2530094
[14]
Salem L G, Warchall J, Mercier P P. A successive approximation recursive digital low-dropout voltage regulator with PD compensation and sub-LSB duty control. IEEE J Solid-State Circuits, 2018, 53, 35 doi: 10.1109/JSSC.2017.2766215
[15]
Huang M, Lu Y, Seng-Pan U, et al. An output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop control. 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, 342
[16]
Huang M, Lu Y, U S P, et al. An analog-assisted tri-loop digital low-dropout regulator. IEEE J Solid-State Circuits, 2018, 53, 20 doi: 10.1109/JSSC.2017.2751512
[17]
Huang M, Lu Y, Lu X. Partial analogue-assisted digital low dropout regulator with transient body-drive and 2.5 × FOM improvement. Electron Lett, 2018, 54, 282 doi: 10.1049/el.2017.4211
[18]
Ma X F, Lu Y, Martins R P, et al. A 0.4 V 430 nA quiescent current NMOS digital LDO with NAND-based analog-assisted loop in 28 nm CMOS. 2018 IEEE International Solid-State Circuits Conference (ISSCC), 2018, 306
[19]
Akram M A, Hong W, Hwang I C. Fast transient fully standard-cell-based all digital low-dropout regulator with 99.97% current efficiency. IEEE Trans Power Electron, 2018, 33, 8011 doi: 10.1109/TPEL.2017.2771942
[20]
Sun X, Boora A, Zhang W B, et al. A 0.6-to-1.1 V computationally regulated digital LDO with 2.79-cycle mean settling time and autonomous runtime gain tracking in 65 nm CMOS. 2019 IEEE International Solid- State Circuits Conference (ISSCC), 2019, 230
[21]
Lee Y J, Jung M Y, Singh S, et al. A 200 mA digital low-drop-out regulator with coarse-fine dual loop in mobile application processors. 2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, 150
[22]
Kim D, Seok M. Fully integrated low-drop-out regulator based on event-driven PI control. 2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, 148
[23]
Otsuga K, Onouchi M, Igarashi Y, et al. An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor. 2012 IEEE International SOC Conference, 2012, 11
[24]
Gangopadhyay S, Somasekhar D, Tschanz J W, et al. A 32 nm embedded, fully-digital, phase-locked low dropout regulator for fine grained power management in digital circuits. IEEE J Solid-State Circuits, 2014, 49, 2684 doi: 10.1109/JSSC.2014.2353798
[25]
Kundu S, Liu M Q, Wen S J, et al. A fully integrated digital LDO with built-in adaptive sampling and active voltage positioning using a beat-frequency quantizer. IEEE J Solid-State Circuits, 2019, 54, 109 doi: 10.1109/JSSC.2018.2870558
[26]
Lee Y H, Peng S Y, Chiu C C, et al. A low quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40 nm SoC for MIPS performance improvement. IEEE J Solid-State Circuits, 2013, 48, 1018 doi: 10.1109/JSSC.2013.2237991
[27]
Yang F, Mok P K T. A nanosecond-transient fine-grained digital LDO with multi-step switching scheme and asynchronous adaptive pipeline control. IEEE J Solid-State Circuits, 2017, 52, 2463 doi: 10.1109/JSSC.2017.2709311
[28]
Lu Y, Huang M, Martins R P. PID control considerations for analog-digital hybrid low-dropout regulators. 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2019, 1
[29]
Kim S T, Shih Y C, Mazumdar K, et al. Enabling wide autonomous DVFS in a 22 nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation. 2015 IEEE International Solid-State Circuits Conference (ISSCC), 2015, 1
[30]
Zhang Y N, Song H X, Zhou R R, et al. A capacitor-less ripple-less hybrid LDO with exponential ratio array and 4000x load current range. IEEE Trans Circuits Syst II, 2019, 66, 36 doi: 10.1109/TCSII.2018.2834899
[31]
Wang X Y, Mercier P P. A dynamically high-impedance charge-pump-based LDO with digital-LDO-like properties achieving a sub-4-fs FoM. IEEE J Solid-State Circuits, 2020, 55, 719 doi: 10.1109/JSSC.2019.2960004
[32]
Nasir S B, Sen S, Raychowdhury A. Switched-mode-control based hybrid LDO for fine-grain power management of digital load circuits. IEEE J Solid-State Circuits, 2018, 53, 569 doi: 10.1109/JSSC.2017.2767183
[33]
Liu X S, Krishnamurthy H K, Na T, et al. A modular hybrid LDO with fast load-transient response and programmable PSRR in 14 nm CMOS featuring dynamic clamp tuning and time-constant compensation. 2019 IEEE International Solid- State Circuits Conference (ISSCC), 2019, 234
[34]
Huang M, Lu Y. An analog-proportional digital-integral multi-loop digital LDO with fast response, improved PSR and zero minimum load current. 2019 IEEE Custom Integrated Circuits Conference (CICC), 2019, 1
[35]
Huang M, Lu Y, Martins R P. An analog-proportional digital-integral multiloop digital LDO with PSR improvement and LCO reduction. IEEE J Solid-State Circuits, 2020, 55, 1637 doi: 10.1109/JSSC.2020.2967540
[36]
Bang S, Lim W, Augustine C, et al. A fully synthesizable distributed and scalable all-digital LDO in 10 nm CMOS. 2020 IEEE International Solid- State Circuits Conference (ISSCC), 2020, 380
[37]
Li Y F, Zhang X Y, Zhang Z, et al. A 0.45-to-1.2-V fully digital low-dropout voltage regulator with fast-transient controller for near/subthreshold circuits. IEEE Trans Power Electron, 2016, 31, 6341 doi: 10.1109/TPEL.2015.2506605
[38]
Oh J, Park J E, Hwang Y H, et al. A 480 mA output-capacitor-free synthesizable digital LDO using CMP-triggered oscillator and droop detector with 99.99% current efficiency, 1.3 ns response time, and 9.8 A/mm2 current density. 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020, 382
[39]
Singh A, Kar M, Chekuri V C K, et al. A digital low-dropout regulator with autotuned PID compensator and dynamic gain control for improved transient performance under process variations and aging. IEEE Trans Power Electron, 2020, 35, 3242 doi: 10.1109/TPEL.2019.2930490
[40]
Ahmed K Z, Krishnamurthy H K, Augustine C, et al. A variation-adaptive integrated computational digital LDO in 22-nm CMOS with fast transient response. IEEE J Solid-State Circuits, 2020, 55, 977 doi: 10.1109/JSSC.2019.2961854
[41]
Lu Y, Yang F, Chen F, et al. A 500 mA analog-assisted digital-LDO-based on-chip distributed power delivery grid with cooperative regulation and IR-drop reduction in 65 nm CMOS. 2018 IEEE International Solid-State Circuits Conference (ISSCC), 2018, 310
[42]
Hershberg B, Weaver S, Sobue K, et al. Ring amplifiers for switched capacitor circuits. IEEE J Solid-State Circuits, 2012, 47, 2928 doi: 10.1109/JSSC.2012.2217865
[43]
Yang F, Mok P K T. A 65 nm inverter-based low-dropout regulator with rail-to-rail regulation and over −20 dB PSR at 0.2 V lowest supply voltage. 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, 106
[44]
Park J E, Hwang J, Oh J, et al. A 0.4-to-1.2 V 0.0057 mm2 55fs-transient-FoM ring-amplifier-based low-dropout regulator with replica-based PSR enhancement. 2020 IEEE International Solid- State Circuits Conference (ISSCC), 2020, 492
[45]
Hazucha P, Karnik T, Bloechel B A, et al. Area-efficient linear regulator with ultra-fast load regulation. IEEE J Solid-State Circuits, 2005, 40, 933 doi: 10.1109/JSSC.2004.842831
[46]
Duong Q H, Nguyen H H, Kong J W, et al. Multiple-loop design technique for high-performance low-dropout regulator. IEEE J Solid-State Circuits, 2017, 52, 2533 doi: 10.1109/JSSC.2017.2717922
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    Received: 25 July 2020 Revised: 26 September 2020 Online: Accepted Manuscript: 30 September 2020Uncorrected proof: 10 October 2020Published: 03 November 2020

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      Mo Huang, Yan Lu, Rui P. Martins. A comparative study of digital low dropout regulators[J]. Journal of Semiconductors, 2020, 41(11): 111405. doi: 10.1088/1674-4926/41/11/111405 M Huang, Y Lu, R P Martins, A comparative study of digital low dropout regulators[J]. J. Semicond., 2020, 41(11): 111405. doi: 10.1088/1674-4926/41/11/111405.Export: BibTex EndNote
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      Mo Huang, Yan Lu, Rui P. Martins. A comparative study of digital low dropout regulators[J]. Journal of Semiconductors, 2020, 41(11): 111405. doi: 10.1088/1674-4926/41/11/111405

      M Huang, Y Lu, R P Martins, A comparative study of digital low dropout regulators[J]. J. Semicond., 2020, 41(11): 111405. doi: 10.1088/1674-4926/41/11/111405.
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      A comparative study of digital low dropout regulators

      doi: 10.1088/1674-4926/41/11/111405
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      • Corresponding author: Email: mohuang@um.edu.mo
      • Received Date: 2020-07-25
      • Revised Date: 2020-09-26
      • Published Date: 2020-11-10

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