| Citation: |
Yin Haifeng, Wang Feng, Liu Jun, Mao Zhigang. A Low Jitter PLL in a 90nm CMOS Digital Process[J]. Journal of Semiconductors, 2008, In Press.
Yin H F, Wang F, Liu J, Mao Z G. A Low Jitter PLL in a 90nm CMOS Digital Process[J]. J. Semicond., 2008, 29(8): 1511.
Export: BibTex EndNote
|
A Low Jitter PLL in a 90nm CMOS Digital Process
-
Abstract
A low jitter phase-locked loop (PLL) that does not need analog resistors and capacitors is designed and fabricated in a 90nm CMOS digital process.The metal parasitic capacitor is used in the PLL loop filter.Test results show that when the PLL is locked on 1.989GHz,the RMS jitter is 3.7977ps,the peak-to-peak jitter is 31.225ps,and the power consumption is about 9mW.The locked output frequency range is from 125MHz to 2.7GHz.-
Keywords:
- PLL,
- PFD,
- charge pump,
- VCO
-
References
-
Proportional views
DownLoad: