Chin. J. Semicond. > 2006, Volume 27 > Issue S1 > 291-294

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SOI Device Design for SEU Hardening

He Wei and Zhang Zhengxuan

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Abstract: A CMOS device design technique based on SOI process,using actively biased isolated wells for single event upset hardening,has been described.Medici and Hspice simulations were performed to simulate inverter constructed by actively biased isolated wells.This paper also discusses the application of this technique.

Key words: SEU SOI CMOS

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    Received: 20 August 2015 Revised: Online: Published: 01 December 2006

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      He Wei, Zhang Zhengxuan. SOI Device Design for SEU Hardening[J]. Journal of Semiconductors, 2006, In Press. He W, Zhang Z X. SOI Device Design for SEU Hardening[J]. Chin. J. Semicond., 2006, 27(13): 291.Export: BibTex EndNote
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      He Wei, Zhang Zhengxuan. SOI Device Design for SEU Hardening[J]. Journal of Semiconductors, 2006, In Press.

      He W, Zhang Z X. SOI Device Design for SEU Hardening[J]. Chin. J. Semicond., 2006, 27(13): 291.
      Export: BibTex EndNote

      SOI Device Design for SEU Hardening

      • Received Date: 2015-08-20

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