Chin. J. Semicond. > 2006, Volume 27 > Issue 12 > 2190-2195

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1.244GHz 0.25μm CMOS Low-Power Phase-Locked Loop

Liu Yongwang, Wang Zhigong and Li Wei

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Abstract: A low-power phase-locked loop (PLL) is designed and fabricated in TSMC’s standard 0.25μm CMOS process.A behavioral simulation method for the PLL’s phase noise is presented.The power consumption of the PLL core is about 12mW.The rms jitter is 6.1ps,and the SSB phase noise is -106dBc/Hz at a 10kHz offset.

Key words: PLLPFDcharge pumpVCO

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    Received: 18 August 2015 Revised: 22 June 2006 Online: Published: 01 December 2006

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      Liu Yongwang, Wang Zhigong, Li Wei. 1.244GHz 0.25μm CMOS Low-Power Phase-Locked Loop[J]. Journal of Semiconductors, 2006, In Press. Liu Y W, Wang Z G, Li W. 1.244GHz 0.25μm CMOS Low-Power Phase-Locked Loop[J]. Chin. J. Semicond., 2006, 27(12): 2190.Export: BibTex EndNote
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      Liu Yongwang, Wang Zhigong, Li Wei. 1.244GHz 0.25μm CMOS Low-Power Phase-Locked Loop[J]. Journal of Semiconductors, 2006, In Press.

      Liu Y W, Wang Z G, Li W. 1.244GHz 0.25μm CMOS Low-Power Phase-Locked Loop[J]. Chin. J. Semicond., 2006, 27(12): 2190.
      Export: BibTex EndNote

      1.244GHz 0.25μm CMOS Low-Power Phase-Locked Loop

      • Received Date: 2015-08-18
      • Accepted Date: 2006-03-19
      • Revised Date: 2006-06-22
      • Published Date: 2006-12-04

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