Chin. J. Semicond. > 2007, Volume 28 > Issue 2 > 176-181

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A 155Mbps 0.5μm CMOS Limiting Amplifier

Jiao Yang, Wang Zhigong, Wang Rong and Guan Zhiqiang

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Abstract: This paper presents a 155Mbps limiting amplifier for STM-1 systems of SDH optical communication.It is implemented in CSMC 0.5μm CMOS technology.Under a supply voltage of 3.3V,it has a power consumption of 198mW.The core of the circuit is composed of 6 cascaded amplifiers that are in a conventional structure of differential pairs,an output buffer,and a DC offset cancellation feedback loop.The small signal gain can be adjusted from 74 to 44dB by an off-chip resistor.The chip was packaged before being tested.The experimental results indicate that the circuit has an input dynamic range of 54dB and provides a single-ended output swing of 950mV.Its output eye diagram remains satisfactory when the pseudo-random bit sequence (PRBS) input speed reaches 400Mbps.

Key words: optical communicationlimiting amplifierCMOS technologySDH

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    Received: 18 August 2015 Revised: 16 October 2006 Online: Published: 01 February 2007

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      Jiao Yang, Wang Zhigong, Wang Rong, Guan Zhiqiang. A 155Mbps 0.5μm CMOS Limiting Amplifier[J]. Journal of Semiconductors, 2007, In Press. Jiao Y, Wang Z G, Wang R, Guan Z Q. A 155Mbps 0.5μm CMOS Limiting Amplifier[J]. Chin. J. Semicond., 2007, 28(2): 176.Export: BibTex EndNote
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      Jiao Yang, Wang Zhigong, Wang Rong, Guan Zhiqiang. A 155Mbps 0.5μm CMOS Limiting Amplifier[J]. Journal of Semiconductors, 2007, In Press.

      Jiao Y, Wang Z G, Wang R, Guan Z Q. A 155Mbps 0.5μm CMOS Limiting Amplifier[J]. Chin. J. Semicond., 2007, 28(2): 176.
      Export: BibTex EndNote

      A 155Mbps 0.5μm CMOS Limiting Amplifier

      • Received Date: 2015-08-18
      • Accepted Date: 2006-08-29
      • Revised Date: 2006-10-16
      • Published Date: 2007-01-30

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