A 10b 40MS/s, 72dB SFDR Pipelined ADC for DTMB Receivers

Yin Xiumei; Wei Qi; Yang Bin; Yang Huazhong

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Article Navigation > Journal of Semiconductors > 2008 > 29(2): 366-370

Yin Xiumei, Wei Qi, Yang Bin, Yang Huazhong. A 10b 40MS/s, 72dB SFDR Pipelined ADC for DTMB Receivers[J]. Journal of Semiconductors, 2008, In Press. Yin X M, Wei Q, Yang B, Yang H Z. A 10b 40MS/s, 72dB SFDR Pipelined ADC for DTMB Receivers[J]. J. Semicond., 2008, 29(2): 366.Export: BibTex EndNote

Citation:

Yin Xiumei, Wei Qi, Yang Bin, Yang Huazhong. A 10b 40MS/s, 72dB SFDR Pipelined ADC for DTMB Receivers[J]. Journal of Semiconductors, 2008, In Press.

Yin X M, Wei Q, Yang B, Yang H Z. A 10b 40MS/s, 72dB SFDR Pipelined ADC for DTMB Receivers[J]. J. Semicond., 2008, 29(2): 366.

Export: BibTex EndNote

Citation:

Yin Xiumei, Wei Qi, Yang Bin, Yang Huazhong. A 10b 40MS/s, 72dB SFDR Pipelined ADC for DTMB Receivers[J]. Journal of Semiconductors, 2008, In Press.

Yin X M, Wei Q, Yang B, Yang H Z. A 10b 40MS/s, 72dB SFDR Pipelined ADC for DTMB Receivers[J]. J. Semicond., 2008, 29(2): 366.

Export: BibTex EndNote

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A 10b 40MS/s, 72dB SFDR Pipelined ADC for DTMB Receivers

Circuits and Systems Laboratory, Department of Electronic Engineering, Tsinghua University, Beijing 100084, China
Circuits and Systems Laboratory, Department of Electronic Engineering, Tsinghua University, Beijing 100084, China
Circuits and Systems Laboratory, Department of Electronic Engineering, Tsinghua University, Beijing 100084, China
Circuits and Systems Laboratory, Department of Electronic Engineering, Tsinghua University, Beijing 100084, China

Received Date: 2015-08-18
Accepted Date: 2007-07-18
Revised Date: 2007-08-30
Published Date: 2008-01-31

Abstract

Abstract

A 10bit 40MS/s pipelined ADC for DTMB receivers is proposed, which saves power by scaling the capacitor size and the OPA current.The measured results indicate that the ADC exhibits an effective number of bits (ENOB) of 9.14 for 4.9MHz input frequency at 40MS/s, and a spurious free dynamic range (SFDR) of 72.3dB.The measured differential and integral nonlinearities of the prototype at the full sampling rate are less than 0.38 least significant bits (LSB) and 0.51 LSB, respectively.The ADC was fabricated in a 0.18μm 1P6M CMOS process, consumes 78mW of power, and occupies 1mm2.
- analog-to-digital converter,
- pipeline analog-to-digital converter,
- spurious free dynamic range

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