Chin. J. Semicond. > 2006, Volume 27 > Issue 7 > 1316-1320

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A Design Technique of Neuron MOS Binary Circuits Based on Multiple-Valued Logic

Hang Guoqiang

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Abstract: A design method for binary neuron MOS circuits employing a summation signal with multiple values is presented.The logical relation of each neuron MOS transistor is formulated using the transmission operation in order to make effective and practical use of the circuits.Using the proposed method,some neuron MOS circuits realizing two-variable common functions and a full adder are designed,and the ratio of the coupling capacitance in each circuit can be calculated conveniently.All the proposed circuits have very simple configurations.Furthermore,the synthesis procedures can be simplified significantly since the voltage signals are added easily by means of floating gates in the neuron MOS transistors.The effectiveness of the proposed approach is validated by HSPICE simulation using TSMC 0.35μm double-polysilicon CMOS technology.

Key words: switching theoryneuron MOS circuitmultiple-input floating-gate MOS circuitthreshold-controllable technique

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    Received: 20 August 2015 Revised: Online: Published: 01 July 2006

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      Hang Guoqiang. A Design Technique of Neuron MOS Binary Circuits Based on Multiple-Valued Logic[J]. Journal of Semiconductors, 2006, In Press. Hang G Q. A Design Technique of Neuron MOS Binary Circuits Based on Multiple-Valued Logic[J]. Chin. J. Semicond., 2006, 27(7): 1316.Export: BibTex EndNote
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      Hang Guoqiang. A Design Technique of Neuron MOS Binary Circuits Based on Multiple-Valued Logic[J]. Journal of Semiconductors, 2006, In Press.

      Hang G Q. A Design Technique of Neuron MOS Binary Circuits Based on Multiple-Valued Logic[J]. Chin. J. Semicond., 2006, 27(7): 1316.
      Export: BibTex EndNote

      A Design Technique of Neuron MOS Binary Circuits Based on Multiple-Valued Logic

      • Received Date: 2015-08-20

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