| Citation: |
Ding Jingfeng, Wang Zhigong, Zhu En, Zhang Li, Wang Gui. 12Gb/s 0.25μm CMOS Low-Power 1∶4 Demultiplexer[J]. Journal of Semiconductors, 2006, In Press.
Ding J F, Wang Z G, Zhu E, Zhang L, Wang G. 12Gb/s 0.25μm CMOS Low-Power 1∶4 Demultiplexer[J]. Chin. J. Semicond., 2006, 27(1): 19.
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12Gb/s 0.25μm CMOS Low-Power 1∶4 Demultiplexer
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Abstract
A low power 12Gb/s single-stage 1∶4 demultiplexer (DEMUX) applied in SONET OC-192 is realized in TSMC’s mix-signal 0.25μm CMOS.All of the circuits are in source coupled FET logic (SCFL) to achieve as high a speed as possible and suppress common mode distortions.This DEMUX is featured for achieving single-stage demultiplexing by using a quarter-rate IQ clock.This method not only reduces the components of the DEMUX but also lowers its power dissipation.The fabricated DEMUX operates error free at 12Gb/s by 231-1 pseudorandom bit sequences in on-wafer testing.The chip size is 0.9mm×0.9mm and the power dissipation is only 210mW with a single 2.5V supply.-
Keywords:
- demultiplexer,
- latch,
- CMOS,
- optical receiver
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References
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Proportional views
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