Abstract: As scaling CMOS device towards sub-30nm gate length,device physics and semiconductor technology will encounter a series of barriers.This paper deeply investigates sub-30nm CMOS key process technologies,especially offers a new low-cost technique for enhancement of hole mobility using strained channel by Ge pre-amorphization implantation (PAI) for S/D extension to overcome the serious short channel effect (SCE) and to improve drive current/off state leakage ratio,which makes 32% hole effective mobility improvement at 0.6MV/cm vertical field for 90nm gate length pMOS.And the hole mobility enhancement strengthens with the scaling down of feature size of the device.The analysis using zero order Laue Zone diffraction on large angle convergent beam electron diffraction (LACBED) in TEM reveal very large compressive strain of -3.6% (gate length 75nm) in the channel region induced by Ge PAI for S/D extension.Based on the optimum of integration technology,high performance gate length 22nm CMOS devices and gate length 27nm CMOS 32 frequency dividers embedded with 57 stage/201 stage CMOS ring oscillator with strained channel are fabricated successfully with EOT 1.2nm and Ni-SALICIDE.

Key words: strained channel, compressive stress, Ge PAI, EOT, gate length, CMOS