| Citation: |
Chen Zuotian, Wu Xuan, Tang Shoulong, Wu Jianhui. CMOS Implementation of a Wideband Low Phase Noise PLL Frequency Synthesizer[J]. Journal of Semiconductors, 2006, In Press.
Chen Z T, Wu X, Tang S L, Wu J H. CMOS Implementation of a Wideband Low Phase Noise PLL Frequency Synthesizer[J]. Chin. J. Semicond., 2006, 27(10): 1838.
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CMOS Implementation of a Wideband Low Phase Noise PLL Frequency Synthesizer
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Abstract
A prototype PLL frequency synthesizer for a single-conversion digital cable TV tuner is integrated in a standard 0.25μm CMOS process, except for the LC tanks and active loop filter.Three-band VCOs with AAC (auto-amplitude control) circuit switches controlled by I2C provide a wideband amplitude stable output.A third order active loop filter is used to boost the tuning voltage.A 16/17 dual-modulus prescaler with on improved logic structure increases the speed.With the help of the system-behavior model of the loop,the design of the loop parameters and the evaluation of the frequency synthesizer are discussed in depth.The measurements results show that the locked range of the frequency synthesizer is 75 to 830MHz,the phase noise in the locked band can reach -90.46dBc/Hz at a 10kHz offset and -115dBc/Hz at a 100kHz offset.The spurious signal near the reference frequency is less than -90dB.-
Keywords:
- :frequency synthesizer,
- phase noise,
- phase-locked loop,
- VCO,
- prescaler
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