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An Integrated Four Quadrant CMOS Analog Multiplier

Huo Mingxue, Tan Xiaoyun, Liu Xiaowei, Wang Yonggang, Ren Lianfeng and Qi Xiangkun

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Abstract: A four quadrant CMOS analog multiplier is presented.It consists of active attenuator and Gilbert cell.The simulation results based on CSMC 0.6μm n well 2p2m process SPICE BSIM3v3 MOS model (level=49) at 0~5V power supply.The simulation results and layout are given.

Key words: analog multiplierGilbert cellCMOS

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    Received: 20 August 2015 Revised: Online: Published: 01 December 2006

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      Huo Mingxue, Tan Xiaoyun, Liu Xiaowei, Wang Yonggang, Ren Lianfeng, Qi Xiangkun. An Integrated Four Quadrant CMOS Analog Multiplier[J]. Journal of Semiconductors, 2006, In Press. Huo M, Tan X Y, Liu X W, Wang Y G, Ren L F, Qi X K. An Integrated Four Quadrant CMOS Analog Multiplier[J]. Chin. J. Semicond., 2006, 27(13): 335.Export: BibTex EndNote
      Citation:
      Huo Mingxue, Tan Xiaoyun, Liu Xiaowei, Wang Yonggang, Ren Lianfeng, Qi Xiangkun. An Integrated Four Quadrant CMOS Analog Multiplier[J]. Journal of Semiconductors, 2006, In Press.

      Huo M, Tan X Y, Liu X W, Wang Y G, Ren L F, Qi X K. An Integrated Four Quadrant CMOS Analog Multiplier[J]. Chin. J. Semicond., 2006, 27(13): 335.
      Export: BibTex EndNote

      An Integrated Four Quadrant CMOS Analog Multiplier

      • Received Date: 2015-08-20

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