| Citation: |
Tang Lu, Wang Zhigong, He Xiaohu, Li Zhiqun, Xu Yong, Li Wei, Guo Feng. Low Jitter,Dual-Modulus Prescalers for RF Receivers[J]. Journal of Semiconductors, 2007, In Press.
Tang L, Wang Z G, He X H, Li Z Q, Xu Y, Li W, Guo F. Low Jitter,Dual-Modulus Prescalers for RF Receivers[J]. Chin. J. Semicond., 2007, 28(12): 1930.
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Low Jitter,Dual-Modulus Prescalers for RF Receivers
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Abstract
Dual-modulus prescalers (DMP) for RF receivers are studied.An improved D-latch is proposed to increase the speed and the driving capability of the DMP.A novel D-latch architecture integrated with ‘OR’ logic is proposed to decrease the complexity of the circuit.A divided-by-16/17 DMP for application in a digital video broadcasting-terrestrial receiver is realized with a TSMC 0.18μm mixed-signal CMOS process.The programmable & pulse swallow divider in this receiver is designed with a 0.18μm CMOS standard cell library and realized in the same process.The measured results show that the DMP has an output jitter of less than 0.03% and works well with the programmable & pulse swallow divider.-
Keywords:
- PLL,
- frequency synthesizer,
- DMP,
- programmable & pulse swallow divider
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References
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Proportional views
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