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A Low Voltage Low Power CMOS 5Gb/s Transceiver

Sun Yehui, Jiang Lixin and Qin Shicai

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Abstract: A low voltage and low power SerDes transceiver implemented in 0.13μm CMOS is described.The power supply voltage is 1V,and the operating frequency range is from 2.5 to 5GHz.The transmitter includes a 20∶1 serializer and a transmission driver,the latter of which uses pre-emphasis architecture for channel compensation.The receiver employs two 1∶20 deserializer,an input signal pre-amplifier,and a clock and data recovery circuit.The pre-amplifier employs a novel architecture,consisting of a feed-forward equalizer to cancel ISI.The measured transceiver power consumption is 127mW/channel.The RMS jitter of the transmitter output is 4ps.Test results indicate the receiver BER is less than 1e-12 when the input signal amplitude is 150mV differential peak to peak and the eye closure is 0.5UI.

Key words: low voltagelow powertransceiverequalization

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    Received: 18 August 2015 Revised: 05 April 2007 Online: Published: 01 August 2007

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      Sun Yehui, Jiang Lixin, Qin Shicai. A Low Voltage Low Power CMOS 5Gb/s Transceiver[J]. Journal of Semiconductors, 2007, In Press. Sun Y H, Jiang L X, Qin S C. A Low Voltage Low Power CMOS 5Gb/s Transceiver[J]. Chin. J. Semicond., 2007, 28(8): 1283.Export: BibTex EndNote
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      Sun Yehui, Jiang Lixin, Qin Shicai. A Low Voltage Low Power CMOS 5Gb/s Transceiver[J]. Journal of Semiconductors, 2007, In Press.

      Sun Y H, Jiang L X, Qin S C. A Low Voltage Low Power CMOS 5Gb/s Transceiver[J]. Chin. J. Semicond., 2007, 28(8): 1283.
      Export: BibTex EndNote

      A Low Voltage Low Power CMOS 5Gb/s Transceiver

      • Received Date: 2015-08-18
      • Accepted Date: 2007-01-11
      • Revised Date: 2007-04-05
      • Published Date: 2007-08-08

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