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Research on a Measurement Circuit for UDSM CMOSProcess Parameter Variation

Yang Yuan, Gao Yong and Yu Ningmei

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Abstract: The main device parameter variations for UDSM processes are discussed briefly.Based on the "amplifying" idea,simple circuits for measuring the gate delay,dynamic power,leakage power,and their variations for a 90nm process are designed.A novel circuit that can get the gate delay variation curve for a UDSM process using shorter inverter link is presented.The circuits are fabricated using 90nm CMOS technology,and the variation curve for the 90nm CMOS process is obtained.The results show that the variation range is 178.6%,194.0% for dynamic power,and 19.5 times for leakage power.Thus the leakage power variation is the most serious.

Key words: ultra deep sub-microngate delaydynamic powerleakage power

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    Received: 18 August 2015 Revised: 30 May 2006 Online: Published: 01 September 2006

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      Yang Yuan, Gao Yong, Yu Ningmei. Research on a Measurement Circuit for UDSM CMOSProcess Parameter Variation[J]. Journal of Semiconductors, 2006, In Press. Yang Y, Gao Y, Yu N M. Research on a Measurement Circuit for UDSM CMOSProcess Parameter Variation[J]. Chin. J. Semicond., 2006, 27(9): 1686.Export: BibTex EndNote
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      Yang Yuan, Gao Yong, Yu Ningmei. Research on a Measurement Circuit for UDSM CMOSProcess Parameter Variation[J]. Journal of Semiconductors, 2006, In Press.

      Yang Y, Gao Y, Yu N M. Research on a Measurement Circuit for UDSM CMOSProcess Parameter Variation[J]. Chin. J. Semicond., 2006, 27(9): 1686.
      Export: BibTex EndNote

      Research on a Measurement Circuit for UDSM CMOSProcess Parameter Variation

      • Received Date: 2015-08-18
      • Accepted Date: 2006-02-14
      • Revised Date: 2006-05-30
      • Published Date: 2006-10-12

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