J. Semicond. > 2008, Volume 29 > Issue 9 > 1764-1769

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Optimization of Global Signal Networks for Island-Style FPGAs

Ni Minghao, Chan S L and Liu Zhongli

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Abstract: We present a staggered buffer connection method that provides flexibility for buffer insertion while designing global signal networks using the tile-based FPGA design methodology.An exhaustive algorithm is used to analyze the trade-off between area and speed of the global signal networks for this staggered buffer insertion scheme,and the criterion for determining the design parameters is presented.The comparative analytic result shows that the methods in this paper are proven to be more efficient for FPGAs with a large array size.

Key words: circuit designFPGAglobal signal networkoptimizationbuffer insertion

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    Received: 18 August 2015 Revised: 18 May 2008 Online: Published: 01 September 2008

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      Ni Minghao, Chan S L, Liu Zhongli. Optimization of Global Signal Networks for Island-Style FPGAs[J]. Journal of Semiconductors, 2008, In Press. Ni M H, Chan S L, Liu Z L. Optimization of Global Signal Networks for Island-Style FPGAs[J]. J. Semicond., 2008, 29(9): 1764.Export: BibTex EndNote
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      Ni Minghao, Chan S L, Liu Zhongli. Optimization of Global Signal Networks for Island-Style FPGAs[J]. Journal of Semiconductors, 2008, In Press.

      Ni M H, Chan S L, Liu Z L. Optimization of Global Signal Networks for Island-Style FPGAs[J]. J. Semicond., 2008, 29(9): 1764.
      Export: BibTex EndNote

      Optimization of Global Signal Networks for Island-Style FPGAs

      • Received Date: 2015-08-18
      • Accepted Date: 2008-02-25
      • Revised Date: 2008-05-18
      • Published Date: 2008-09-03

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