Energy levels of a donor impurity in the ZnO parabolic quantum well under the magnetic field are investigated using the variational method. The binding energy of the ground state, the energies of 2p± state and 1s→2p± transition energies of a hydrogenic donor in the ZnO parabolic quantum well are numerically calculated as a function of the strength of magnetic field for different parabolic potential fields. The results show that the external magnetic field has an obvious influence on the binding energies and the 1s → 2p± transition energies of a hydrogenic donor. The 1s to 2p± transition energy increases linearly with the strength of magnetic field, but the 1s to 2p_ transition energy decreases when the strength of magnetic field increases for the small field strength. Compared to the GaAs parabolic well, the donors are more tightly bound to the ZnO parabolic well and the influence of external magnetic field on the binding energy of a donor is much stronger in the ZnO parabolic well.

Semiconducting Mg₂Si films were synthesized on silicon (111) substrates by magnetron sputtering deposition and subsequent annealing in an annealing furnace filled with argon gas, and the effects of heat treatment on the formation and microstructure of Mg₂Si films were investigated. The structural and morphological properties were investigated by X-ray diffraction (XRD) and scanning electron microscopy (SEM), respectively. The results show that the crystal quality of Mg₂Si films depends strongly on the annealing temperature, the annealing time and the deposited magnesium film thickness. Annealing at 400 ℃ for 5 h is optimal for the preparation of Mg₂Si film. XRD and SEM results show that magnesium silicide film with various orientations is formed on the silicon surface because of the interdiffusion and reaction of magnesium with substrate silicon atoms, and the evolution of surface features on growing films is very dependent on the annealing temperature and time.

Molecular beam epitaxy growth of a bilayer stacked InAs/GaAs quantum dot structure on a pure GaAs matrix has been systemically investigated. The influence of growth temperature and the InAs deposition of both layers on the optical properties and morphologies of the bilayer quantum dot (BQD) structures is discussed. By optimizing the growth parameters, InAs BQD emission at 1.436 μm at room temperature with a narrower FWHM of 27 meV was demonstrated. The density of QDs in the second layer is around 9 × 10⁹ to 1.4 × 10¹⁰ cm^-2. The BQD structure provides a useful way to extend the emission wavelength of GaAs-based material for quantum functional devices.

InGaN films were deposited on (0001) sapphire substrates with GaN buffer layers under different growth temperatures by metalorganic chemical vapor deposition. The In-composition of InGaN film was approximately controlled by changing the growth temperature. The connection between the growth temperature, In content, surface morphology and defect formation was obtained by X-ray diffraction, scanning electron microscopy (SEM) and atomic force microscopy (AFM). Meanwhile, by comparing the SEM and AFM surface morphology images, we proposed several models of three different defects and discussed the mechanism of formation. The prominent effect of higher growth temperature on the quality of the InGaN films and defect control were found by studying InGaN films at various growth temperatures.

Electrical properties of In_xAl_1-xN/AlN/GaN structure are investigated by solving coupled Schrödinger and Poisson equations self-consistently. The variations in internal polarizations in In_xAl_1-xN with indium contents are studied and the total polarization is zero when the indium content is 0.41. Our calculations show that the two-dimensional electron gas (2DEG) sheet density will decrease with increasing indium content. There is a critical thickness for AlN. The 2DEG sheet density will increase with In_xAl_1-xN thickness when the AlN thickness is less than the critical value. However, once the AlN thickness becomes greater than the critical value, the 2DEG sheet density will decrease with increasing barrier thickness. The critical value of AlN is 2.8 nm for the lattice-matched In_0.18Al_0.82N/AlN/GaN structure. Our calculations also show that the critical value decreases with increasing indium content.

Nc-Si/SiO₂ multilayers were fabricated on silicon wafers in a plasma enhanced chemical vapour deposition system using in situ oxidation technology, followed by three-step thermal treatments. Carrier transportation at room temperature is characterized by current voltage measurement, and negative different conductances can be observed both under forward and negative biases, which is explained by resonant tunnelling. The resonant tunnelling peak voltage is related to the thicknesses of the nc-Si and SiO₂ sublayers. And the resonant tunnelling peak voltage under negative bias is larger than that under forward bias. An energy band diagram and an equivalent circuit diagram were constructed to analyze and explain the above transportation process and properties.

This paper describes a technique that can obtain ternary Sn–Ag–In solder bumps with fine pitch and homogenous composition distribution. The main feature of this process is that tin-silver and indium are electroplated on copper under bump metallization (UBM) in sequence. After an accurate reflow process, Sn_1.8Ag_9.4In solder bumps are obtained. It is found that the intermetallic compounds (IMCs) between Sn–Ag–In solder and Cu grow with the reflow time, which results in an increase in Ag concentration in the solder area. So during solidification, more Ag₂In nucleates and strengthens the solder.

A two-dimensional model of a 4H-SiC metal–semiconductor–metal (MSM) ultraviolet photodetector has been established using a self-consistent numerical calculation method. The structure-dependent spectral response of a 4H-SiC MSM detector is calculated by solving Poisson's equation, the current continuity equation and the current density equation. The calculated results are verified with experimental data. With consideration of the reflection and absorption on the metal contacts, a detailed study involving various electrode heights (H), spacings (S) and widths (W) reveals conclusive results in device design. The mechanisms responsible for variations of responsivity with those parameters are analyzed. The findings show that responsivity is inversely proportional to electrode height and is enhanced with an increase of electrode spacing and width. In addition, the ultraviolet (UV)-to-visible rejection ratio is > 10³. By optimizing the device structure at 10 V bias, a responsivity as high as 180.056 mA/W, a comparable quantum efficiency of 77.93% and a maximum UV-to-visible rejection ratio of 1875 are achieved with a detector size of H = 50 nm, S = 9 μm and W = 3 μm.

In order to quantitatively compare the design cost and performance of various gate styles, NMOS transistors with two-edged, annular and ring gate layouts were designed and fabricated by a commercial 0.35 μm CMOS process. By comparing the minimum W/L ratios and transistor areas, it was found that either the annular layout or its ring counterpart incurs a higher area penalty that depends on the W/L ratio of the transistor to be designed. Furthermore, by comparing the output and transfer characteristics of the transistors and analyzing the popular existing methods for extracting the effective W/L ratio, it was shown that the mid-line approximation for annular NMOS could incur an error of more than 10%. It was also demonstrated that the foundry-provided extraction tool needs significant adaptation when being applied to the enclosed-gate transistors, since it is targeted only toward the two-edged transistor. A simple approach for rough extraction of the W/L ratio for the ring-gate NMOS was presented and its effectiveness was confirmed by the experimental results with an error up to 8%.

Deviation of threshold voltage and effective mobility due to random dopant fluctuation is proposed. An improved 65 nm average drain current MOS model called α law is utilized after fitting HSPICE simulating data and extracting process parameters. Then, a current mismatch model of nanoscale MOSFETs induced by random dopant fluctuation is presented based on propagation of variation theory. In test conditions, the calculated standard deviation applying this model, compared to 100 times Monte–Carlo simulation data with HSPICE, indicates that the average relative error and relative standard deviation is 0.24% and 0.22%, respectively. The results show that this mismatch model is effective to illustrate the physical mechanism, as well as being simple and accurate.

The factors influencing the current–voltage (I–V) characteristics of light-emitting diodes (LEDs) are investigated to reveal the connection of I–V characteristics under optical excitation and those under electrical excitation. By inspecting the I–V curves under optical and electrical excitation at identical injection current, it has been found that the I–V curves exhibit apparent differences in voltage values. Furthermore, the differences are found to originate from the junction temperatures in diverse excitation ways. Experimental results indicate that if the thermal effect of illuminating spot is depressed to an ignorable extent by using pulsed light, the junction temperature will hardly deflect from that under optical excitation, and then the I–V characteristics under two diverse excitation ways will be the same.

Silicon nanowire arrays (SiNWAs) are fabricated on polished pyramids of textured Si using an aqueous chemical etching method. The silicon nanowires themselves or hybrid structures of nanowires and pyramids both show strong anti-reflectance abilities in the wavelength region of 300–1000 nm, and reflectances of 2.52% and less than 8% are achieved, respectively. A 12.45% SiNWAs-textured solar cell (SC) with a short circuit current of 34.82 mA/cm² and open circuit voltage (V_oc) of 594 mV was fabricated on 125 × 125 mm² Si using a conventional process including metal grid printing. It is revealed that passivation is essential for hybrid structure textured SCs, and V_oc can be enlarged by 28.6% from 420 V to 560 mV after the passivation layer is deposited. The loss mechanism of SiNWA SC was investigated in detail by systematic comparison of the basic parameters and external quantum efficiency (EQE) of samples with different fabrication processes. It is proved that surface passivation and fabrication of a metal grid are critical for high efficiency SiNWA SC, and the performance of SiNWA SC could be improved when fabricated on a substrate with an initial PN junction.

The sensitivities of betavoltaic batteries and photovoltaic batteries to series and parallel resistance are studied. Based on the study, an electrode pattern design principle of GaAs betavoltaic batteries is proposed. GaAs PIN junctions with and without the proposed electrode pattern are fabricated and measured under the illumination of ⁶³Ni. Results show that the proposed electrode can reduce the backscattering and shadowing for the beta particles from ⁶³Ni to increase the GaAs betavoltaic battery short circuit currents effectively but has little impact on the fill factors and ideal factors.

Micro ring resonator (MRR) filters based on a silicon on insulator (SOI) nanowire waveguide are fabricated by electron beam photolithography (EBL) and inductive coupled plasma (ICP) etching technology. The cross-section size of the strip waveguides is 450 × 220 nm², and the bending radius of the micro ring is around 5 μm. The test results from the tunable filter based on a single ring show that the free spectral range (FSR) is 16.8 nm and the extinction ratio (ER) around the wavelength 1550 nm is 18.1 dB. After thermal tuning, the filter's tuning bandwidth reaches 4.8 nm with a tuning efficiency of 0.12 nm/℃ Meanwhile, we fabricated and studied multi-channel filters based on a single ring and a double ring. After measurement, we drew the following conclusions: during the signal transmission of multi-channel filters, crosstalk exists mainly among different transmission channels and are fairly distinct when there are signals input to add ports.

A high power density monolithic power amplifier operated at Ku band is presented utilizing a 0.3 μm AlGaN/GaN HEMT production process on a 2-inch diameter semi-insulating (SI) 4H-SiC substrate by MOCVD. Over the 12–14 GHz frequency range, the single chip amplifier demonstrates a maximum power of 38 dBm (6.3 W), a peak power added efficiency (PAE) of 24.2% and linear gain of 6.4 to 7.5 dB under a 10% duty pulse condition when operated at V_ds = 25 V and V_gs = –4 V. At these power levels, the amplifier exhibits a power density in excess of 5 W/mm.

A new, low complexity, ultra-wideband 3.1–10.6 GHz low noise amplifier (LNA), designed in a chartered 0.18 μm RFCMOS technology, is presented. The ultra-wideband LNA consists of only two simple amplifiers with an inter-stage inductor connected. The first stage utilizing a resistive current reuse and dual inductive degeneration technique is used to attain a wideband input matching and low noise figure. A common source amplifier with an inductive peaking technique as the second stage achieves high flat gain and wide –3 dB bandwidth of the overall amplifier simultaneously. The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB, and a high reverse isolation of - 45 dB, and good input/output return losses are better than –10 dB in the frequency range of 3.1–10.6 GHz. An excellent noise figure (NF) of 2.8–4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V. An input-referred third-order intercept point (IIP3) is –7.1 dBm at 6 GHz. The chip area, including testing pads, is only 0.8 × 0.9 mm².

A 14-bit low power self-timed differential successive approximation (SAR) ADC with an on-chip multi-segment bandgap reference (BGR) is described. An on-chip multi-segment BGR, which has a temperature coefficient of 1.3 ppm/℃ and a thermal drift of about 100 μV over the temperature range of –40 to 120 ℃ is implemented to provide a high precision reference voltage for the SAR ADC. The Gray code form is utilized instead of binary form mode control to reduce substrate noise and enhance the linearity of the whole system. Self-timed bit-cycling is adopted to enhance the time efficiency. The 14-bit ADC was fabricated in a TSMC 0.13 μm CMOS process. With the on-chip BGR, the SAR ADC achieves an SNDR of 81.2 dB (13.2 ENOB) and an SFDR of 85.2 dB with a conversion rate of 2 MS/s at room temperature and can keep an ENOB of more than 12 bits at a conversion rate of 2 MS/s over the temperature range from –40 to 120 ℃.

This paper provides a mixed continuous-time/discrete-time, single-loop, 4th-order, 4-bit audio-band sigma delta ADC with capacitor digital self-calibration for RC spread compensation. This ADC combines the benefits of CT and DT circuits, and the self-calibration control circuits compensate for the variation of the RC product in the continuous-time integrator and for variation in the sampling frequency. Measurement results show that the peak SNR of this ADC reaches 102 dB and the total power consumption is less than 30 mW.

A novel low-offset dynamic comparator for high-speed low-voltage analog-to-digital converters (ADCs) has been proposed. In the proposed comparator, a CMOS switch takes the place of the dynamic current sources in the differential comparator, which allows the differential input transistors still to operate in the saturation region at the comparing time. This gives the proposed comparator a low offset as the differential comparator while tolerating a sub-1-V supply voltage. Additionally, it also features a larger input swing, less sensitivity to common mode voltage, and a simple relationship between the input and reference voltage. This proposed comparator with two traditional comparators has been realized by SMIC 0.13 μm CMOS technology. The contrast experimental results verify these advantages over conventional comparators. It has been used in a 12-bit 100-MS/s pipeline ADC.

A phase-locked loop (PLL) frequency synthesizer with a novel phase-switching prescaler and a high-Q LC voltage controlled oscillator (VCO) is presented. The phase-switching prescaler with a novel modulus control mechanism is much more robust on process variations. The Q factor of the inductor, I-MOS capacitors and varactors in the VCO are optimized. The proposed frequency synthesizer was fabricated by SMIC 0.13 μm 1P8M MMRF CMOS technology with a chip area of 1150 × 2500 μm². When locking at 5 GHz, the current consumption is 15 mA from a supply voltage of 1.2 V and the measured phase noise at a 1 MHz offset is –122.45 dBc/Hz.

A transient performance optimized CCL-LDO regulator is proposed. In the CCL-LDO, the control method of the charge pump phase-locked loop is adopted. A current control loop has the feedback signal and reference current to be compared, and then a loop filter generates the gate voltage of the power MOSFET by integrating the error current. The CCL-LDO has the optimized damping coefficient and natural resonant frequency, while its output voltage can be sub-1-V and is not restricted by the reference voltage. With a 1 μF decoupling capacitor, the experimental results based on a 0.13 μm CMOS process show that the output voltage is 1.0 V; when the workload changes from 100 μA to 100 mA transiently, the stable dropout is 4.25 mV, the settling time is 8.2 μs and the undershoot is 5.11 mV; when the workload changes from 100 mA to 100 μA transiently, the stable dropout is 4.25 mV, the settling time is 23.3 μs and the overshoot is 6.21 mV. The PSRR value is more than - 95 dB. Most of the attributes of the CCL-LDO are improved rapidly with a FOM value of 0.0097.

A CMOS wideband front-end IC is demonstrated in this paper. It consists of a low noise transconductance amplifier (LNTA) and a direct RF sampling mixer (DSM) with embedded programmable discrete-time filtering. The LNTA has the features of 0.5–6 GHz wideband, wideband input matching and low noise. The embedded filter following the DSM operates in discrete-time charge domain, filtering the aliasing signals and interferences while controlling the IF bandwidth according to the clock frequency. The measured NF of the front-end was below 7 dB throughout the whole band from 0.5 to 6 GHz. It shows a conversion gain of 12.6 dB and IP_1dB of -7.5 dBm at 2.4 GHz. It occupies a chip area of 0.23 mm² and consumes 14 mA DC current.

This paper describes a CMOS voltage reference using only resistors and transistors working in weak inversion, without the need for any bipolar transistors. The voltage reference is designed and fabricated by a 0.18 μm CMOS process. The experimental results show that the proposed voltage reference has a temperature coefficient of 370 ppm/℃ at a 0.8 V supply voltage over the temperature range of –35 to 85 ℃ and a 0.1% variation in supply voltage from 0.8 to 3 V. Furthermore, the supply current is only 1.5 μA at 0.8 V supply voltage.

A highly linear, high output power, 0.13 μm CMOS direct conversion transmitter for wideband code division multiple access (WCDMA) is described. The transmitter delivers 6.8 dBm output power with 38 mA current consumption. With careful design on the resistor bank in the IQ-modulator, the gain step accuracy is within 0.1 dB, hence the image rejection ratio can be kept below -47 dBc for the entire output range. The adjacent channel leakage ratio and the LO leakage at 6.8 dBm output power are -44 dBc @ 5 MHz and –37 dBc, respectively, and the corresponding EVM is 3.6%. The overall gain can be programmed in 6 dB steps in a 66-dB range.

A Ka-band GaN amplifier MMIC has been designed in CPW technology, and fabricated with a domestic GaN epitaxial wafer and process. This is, to the best of our knowledge, the first demonstration of domestic Ka-band GaN amplifier MMICs. The single stage CPW MMIC utilizes an AlGaN/GaN HEMT with a gate-length of 0.25 μm and a gate-width of 2 × 75 μm. Under V_ds = 10 V, continuous-wave operating conditions, the amplifier has a 1.5 GHz operating bandwidth. It exhibits a linear gain of 6.3 dB, a maximum output power of 22 dBm and a peak PAE of 9.5% at 26.5 GHz. The output power density of the AlGaN/GaN HEMT in the MMIC reaches 1 W/mm at Ka-band under the condition of V_ds = 10 V.

We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 10⁵ rad(Si), dose rate survivability of 1.5 × 10¹¹ rad(Si)/s and neutron fluence immunity of 1 × 10¹⁴ n/cm².

This paper presents a CML transceiver for a PCI-express generation 2 physical layer protocol that has been fabricated by SMIC's 0.13 μm CMOS technology. The active area of the transceiver is 0.016 mm² and it consumes a total of 150 mW power at a 1.2 V supply voltage. The transmitter uses two stage pre-emphasis circuits with active inductors, reducing inter-symbol interference and extended bandwidth；the receiver uses a time-domain adaptive equalizer, the circuit uses an inductive peaking technique and extends the bandwidth, and the use of active inductors reduces the circuit area and power consumption effectively. The measurement results show that this circuit could stably transmit the signal at the data rate of 5 Gbps, the output signal swing of the transmitter is 350 mV with jitter of 14 ps, the eye opening of the receiver is 135 mV and the eye width is 0.56 UI. The circuit performance sufficiently meets the requirements of the PCI-Express 2.0 protocol.

Abstract: Two different LNA design techniques, namely the classical two-port technique and Shaeffer’s technique, have been introduced, compared and implemented for practical design. Their merits and drawbacks are also discussed. The paper mainly focuses on the former technique, which is seldom introduced in traditional papers. Since a parasitic capacitor of transistor is included in the computation of the former technique, the errors caused by the ignorance of the capacitor have been minimized, which is superior to traditional techniques. Using the former technique, a fully integrated LNA is realized with only 1.4dB while drawing 1.3 mA DC at 2.4 GHz for simulation results. Another version of LNA is designed using the latter technique, which has been fabricated.

In the sub-wavelength regime, design for manufacturability (DFM) becomes increasingly important for field programmable gate arrays (FPGAs). In this paper, an automated tile generation flow targeting micro-regular fabric is reported. Using a publicly accessible, well-documented academic FPGA as a case study, we found that compared to the tile generators previously reported, our generated micro-regular tile incurs less than 10% area overhead, which could be potentially recovered by process window optimization, thanks to its superior printability. In addition, we demonstrate that on 45 nm technology, the generated FPGA tile reduces lithography induced process variation by 33%, and reduce probability of failure by 21.2%. If a further overhead of 10% area can be recovered by enhanced resolution, we can achieve the variation reduction of 93.8% and reduce the probability of failure by 16.2%.