| Citation: |
Gong Na, Wang Jinhui, Guo Baozeng, Wang Yongqing, Cao Xiaobing, Tian Xiuli. Robustness aware high performance high fan-in domino OR logic design[J]. Journal of Semiconductors, 2009, 30(6): 065005. doi: 10.1088/1674-4926/30/6/065005
Gong N, Wang J H, Guo B Z, Wang Y Q, Cao X B, Tian X L. Robustness aware high performance high fan-in domino OR logic design[J]. J. Semicond., 2009, 30(6): 065005. doi: 10.1088/1674-4926/30/6/065005.
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Robustness aware high performance high fan-in domino OR logic design
doi: 10.1088/1674-4926/30/6/065005
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Abstract
A novel technique using a keeper with a simultaneous low supply voltage and low body voltage is proposed to improve the overall performance of high fan-in OR gates without modifying the physical dimensions of the keeper. Simulation results of a 16-input domino OR gate using 45 nm CMOS technology show that the proposed technique could trade off between a high power/speed efficient operation and the robustness to noise effectively. Also, a Monte Carlo analysis indicates that the proposed domino OR gate is more robust to parameter variation compared to a conventional domino OR gate.-
Keywords:
- Domino OR,
- robustness,
- power consumption,
- parameter variation
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References
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Proportional views
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