SEMICONDUCTOR INTEGRATED CIRCUITS

Optimization design of a full asynchronous pipeline circuit based on null convention logic

Guan Xuguang, Zhou Duan and Yang Yintang

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Abstract: This paper proposes a new optimization method to improve the performance of a null convention logic asynchronous pipeline. Parallel combinational logic modules in the pipelines can work alternately in null and data cycles by using a parallel processing mode. The complete waiting time for both null and data signals of combinational logic output in previous asynchronous register stage is reduced by decoupling the output from combinational logic modules. Performance penalty brought by null cycle is reduced while the data processing capacity is increased. The novel asynchronous pipeline based on asynchronous full adders with different bit widths as asynchronous combination logic modules is simulated using 0.18-μm CMOS technology. Based on 6 bits asynchronous adder as asynchronous combination logic modules, the simulation result of this new pipeline proposal demonstrates a high throughput up to 72.4% improvement with appropriate power consumption. This indicates the new design proposal is preferable for high-speed asynchronous designs due to its high throughput and delay-insensitivity.

Key words: NCL asynchronous circuit self-timed circuit high-speed asynchronous pipelineparallel processing

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    Received: 18 August 2015 Revised: 26 February 2009 Online: Published: 01 July 2009

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      Guan Xuguang, Zhou Duan, Yang Yintang. Optimization design of a full asynchronous pipeline circuit based on null convention logic[J]. Journal of Semiconductors, 2009, 30(7): 075010. doi: 10.1088/1674-4926/30/7/075010 Guan X G, Zhou D, Yang Y T. Optimization design of a full asynchronous pipeline circuit based on null convention logic[J]. J. Semicond., 2009, 30(7): 075010. doi: 10.1088/1674-4926/30/7/075010.Export: BibTex EndNote
      Citation:
      Guan Xuguang, Zhou Duan, Yang Yintang. Optimization design of a full asynchronous pipeline circuit based on null convention logic[J]. Journal of Semiconductors, 2009, 30(7): 075010. doi: 10.1088/1674-4926/30/7/075010

      Guan X G, Zhou D, Yang Y T. Optimization design of a full asynchronous pipeline circuit based on null convention logic[J]. J. Semicond., 2009, 30(7): 075010. doi: 10.1088/1674-4926/30/7/075010.
      Export: BibTex EndNote

      Optimization design of a full asynchronous pipeline circuit based on null convention logic

      doi: 10.1088/1674-4926/30/7/075010
      • Received Date: 2015-08-18
      • Accepted Date: 2008-11-17
      • Revised Date: 2009-02-26
      • Published Date: 2009-07-10

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