SEMICONDUCTOR INTEGRATED CIRCUITS

Design for an IO block array in a tile-based FPGA

Ding Guangxin, Chen Lingdou and Liu Zhongli

+ Author Affiliations

PDF

Abstract: A design for an IO block array in a tile-based FPGA is presented. Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers. Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area. The local routing pool increases the flexibility of routing and the routability of the whole FPGA. An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards. The organization of the IO block array is described in an architecture descriptionfile, from which the array layout can be accomplished through use of an automated layout assembly tool. This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series. The bond-out schemes of the same FPGA chip in different packages are also considered. The layout is based on SMIC 0.13 µm logic 1P8M salicide 1.2/2.5 V CMOS technology. Our performance is comparable with commercial SRAM-based FPGAs which use a similar process.

Key words: FPGA; IO block; signal path; configurable IO buffer; layout; packaging

  • Search

    Advanced Search >>

    GET CITATION

    shu

    Export: BibTex EndNote

    Article Metrics

    Article views: 3766 Times PDF downloads: 1330 Times Cited by: 0 Times

    History

    Received: 18 August 2015 Revised: 06 April 2009 Online: Published: 01 August 2009

    Catalog

      Email This Article

      User name:
      Email:*请输入正确邮箱
      Code:*验证码错误
      Ding Guangxin, Chen Lingdou, Liu Zhongli. Design for an IO block array in a tile-based FPGA[J]. Journal of Semiconductors, 2009, 30(8): 085008. doi: 10.1088/1674-4926/30/8/085008 Ding G X, Chen L D, Liu Z L. Design for an IO block array in a tile-based FPGA[J]. J. Semicond., 2009, 30(8): 085008. doi:  10.1088/1674-4926/30/8/085008.Export: BibTex EndNote
      Citation:
      Ding Guangxin, Chen Lingdou, Liu Zhongli. Design for an IO block array in a tile-based FPGA[J]. Journal of Semiconductors, 2009, 30(8): 085008. doi: 10.1088/1674-4926/30/8/085008

      Ding G X, Chen L D, Liu Z L. Design for an IO block array in a tile-based FPGA[J]. J. Semicond., 2009, 30(8): 085008. doi:  10.1088/1674-4926/30/8/085008.
      Export: BibTex EndNote

      Design for an IO block array in a tile-based FPGA

      doi: 10.1088/1674-4926/30/8/085008
      • Received Date: 2015-08-18
      • Accepted Date: 2009-03-09
      • Revised Date: 2009-04-06
      • Published Date: 2009-07-31

      Catalog

        /

        DownLoad:  Full-Size Img  PowerPoint
        Return
        Return