Abstract: A novel scalable model for multi-finger RF MOSFETs modeling is presented. All the parasitic components, including gate resistance, substrate resistance and wiring capacitance, are directly determined from the layout. This model is further verified using a standard 0.13 μm RF CMOS process with nMOSFETs of different numbers of gate fingers, with the per gate width fixed at 2.5 μm and the gate length at 0.13 μm. Excellent agreement between measured and simulated S-parameters from 100 MHz to 20 GHz demonstrate the validity of this model.

Key words: RF-MOSFET, scalable model, parasitic components, layout-based