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Spacing optimization of high power LED arrays for solid state lighting

Y. Sing Chan and S. W. Ricky Lee

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Abstract: This paper provides an analytical approach to determine the optimum pitch by utilizing a thermal resistance network, under the assumption of constant luminous efficiency. This work allows an LED array design which is mounted on a printed circuit board (PCB) attached with a heat sink subject to the natural convection cooling. Being validated by finite element (FE) models, the current approach can be shown as an effective method for the determination of optimal component spacing in an LED array assembly for SSL.

Key words: high power LEDthermal resistance networkfinite element modeling

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    Received: 18 August 2015 Revised: Online: Published: 01 January 2011

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      Y. Sing Chan, S. W. Ricky Lee. Spacing optimization of high power LED arrays for solid state lighting[J]. Journal of Semiconductors, 2011, 32(1): 014005. doi: 10.1088/1674-4926/32/1/014005 Y S Chan, S W R Lee. Spacing optimization of high power LED arrays for solid state lighting[J]. J. Semicond., 2011, 32(1): 014005. doi:  10.1088/1674-4926/32/1/014005.Export: BibTex EndNote
      Citation:
      Y. Sing Chan, S. W. Ricky Lee. Spacing optimization of high power LED arrays for solid state lighting[J]. Journal of Semiconductors, 2011, 32(1): 014005. doi: 10.1088/1674-4926/32/1/014005

      Y S Chan, S W R Lee. Spacing optimization of high power LED arrays for solid state lighting[J]. J. Semicond., 2011, 32(1): 014005. doi:  10.1088/1674-4926/32/1/014005.
      Export: BibTex EndNote

      Spacing optimization of high power LED arrays for solid state lighting

      doi: 10.1088/1674-4926/32/1/014005
      • Received Date: 2015-08-18

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